摘要： 为实现USB 3.0设备的单芯片应用,提出一种可配置的USB 3.0设备控制器架构和面向SoC集成的IP核设计方法。通过宏定义和寄存器IP配置,使得USB 3.0设备控制器支持系统总线、物理层接口、端点属性、缓冲以及低功耗策略可配,提高IP重用性。采用门控时钟技术对非工作状态逻辑进行时钟屏蔽以降低动态功耗,利用门控电源技术断开USB控制器电源,从而最大限度地降低挂起模式下的静态功耗。实验结果表明,使用门控时钟、门控电源技术后,USB 3.0设备控制器在U0状态下的动态功耗减少50%、在休眠模式下的总功耗比U3状态减少95.5%。
关键词:
USB 3.0协议,
IP核,
可配置,
低功耗,
门控时钟,
门控电源
Abstract: To implement the single chip for USB 3.0 device application,a configurable architecture of USB 3.0 device controller and a design method of SoC-integration-oriented IP core are proposed.The controller is configurable on system buses,physical interfaces,endpoint properties,buffers and low-power strategies through macro definition and IP configuration of register,and it can improve the IP reusability.Clock gating is used to reduce the dynamic power consumption of idle logic while power gating is used to reduce the utmost static power consumption of controller in suspend mode.Experimental results show that,by using clock gating,the dynamic power consumption of the controller is reduced by 50% in U0,by using power gating,the total power consumption of the controller is reduced by 95.5% in hibernation mode compared with U3.
Key words:
USB 3.0 protocol,
IP core,
configurable,
low-power,
clock gating,
power gating
中图分类号:
黄凯,林威,蒋进松,胡腾,修思文,严晓浪. 低功耗可配置的USB 3.0设备控制器IP核设计[J]. 计算机工程, doi: 10.3969/j.issn.1000-3428.2015.12.001.
HUANG Kai,LIN Wei,JIANG Jinsong,HU Teng,XIU Siwen,YAN Xiaolang. Design of Low-power and Configurable IP Core for USB 3.0 Device Controller[J]. Computer Engineering, doi: 10.3969/j.issn.1000-3428.2015.12.001.