计算机工程

• 体系结构与软件技术 • 上一篇    下一篇

一种高效片间互联接口协议的设计与实现

李沛南 1,2,薛萍 1,林忱 2,蒋银坪 2,孟洪宇 2   

  1. (1.哈尔滨理工大学 自动化学院,哈尔滨 150080; 2.中国科学院自动化研究所,北京 100190)
  • 收稿日期:2017-03-03 出版日期:2018-04-15 发布日期:2018-04-15
  • 作者简介:李沛南(1993—),男,硕士研究生,主研方向为片上系统;薛萍,教授、博士;林忱,博士;蒋银坪,硕士;孟洪宇,博士研究生。
  • 基金项目:
    中科院A类先导专项NICT重大项目“代数处理器芯片”(XDA06011000)。

Design and Implementation of an Effective Chip-to-chip Interconnection Protocol

LI Peinan  1,2,XUE Ping  1,LIN Chen  2,JIANG Yinping  2,MENG Hongyu  2   

  1. (1.School of Automation,Harbin University of Science and Technology,Harbin 150080,China;2.Institute of Automation,Chinese Academy of Sciences,Beijing 100190,China)
  • Received:2017-03-03 Online:2018-04-15 Published:2018-04-15

摘要: 传统接口互联协议由于复杂的路由结构,使得传输效率较低。为此,提出一种分层的点对点串行传输接口协议。采用分层架构提升灵活性和可扩展性,在硬件上实现循环冗余校验,从而提升传输可靠性,选取串行传输模块减小芯片面积并提升传输效率。实验结果表明,与PCI-Express和SRIO相比,该协议接口面积小、有效带宽高、传输延时低。

关键词: 片间互联, 点对点结构, 低延迟, 高带宽, 现场可编程门阵列

Abstract: Complex routing architecture in traditional chip-to-chip interconnect protocols always result in low operating frequency.Therefore,this paper proposes a multi-layer point-to-point serial interconnect protocol.The protocol employs layered architecture to improve the flexibility and scalability,cyclic redundancy check implemented in hardware to enhance reliability,and serial transmission module to reduce the area penalty and improve efficiency.Compared with PCI-Express and SRIO,experimental results show that the protocol has the features of low area,high bandwidth and low latency.

Key words: chip-to-chip interconnection, point-to-point structure, low latency, high bandwidth, Field Programmable Gate Array(FPGA)

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