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计算机工程 ›› 2010, Vol. 36 ›› Issue (8): 227-229. doi: 10.3969/j.issn.1000-3428.2010.08.080

• 工程应用技术与实现 • 上一篇    下一篇

流水线配置技术在可重构处理器中的应用

于苏东,刘雷波,魏少军   

  1. (清华大学信息科学与技术国家实验室清华大学微电子所,北京 100084)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2010-04-20 发布日期:2010-04-20

Application of Pipeline Reconfiguration Technique in Reconfigurable Processor

YU Su-dong, LIU Lei-bo, WEI Shao-jun   

  1. (National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084)
  • Received:1900-01-01 Revised:1900-01-01 Online:2010-04-20 Published:2010-04-20

摘要: 提出一种应用于可重构处理器中的流水线配置技术,能够有效减低配置时间,提高应用程序的执行速度。可重构处理器包括通用处理器和一个粗颗粒度的可重构阵列。可重构阵列将处理应用中占据大量执行时间的循环,这些循环将被分解为不同的行在阵列上以流水线的方式执行。该技术在FPGA验证系统上得到了验证。验证的应用包括H.264基准中的整数离散余弦变换和运动估计。相比传统的可重构处理器PipeRench, MorphoSys以及TI的DSP TMS320DM642有大约3.5倍的性能提升。

关键词: 可重构处理器, 循环映射, 流水线配置

Abstract: This paper proposes a novel pipeline reconfiguration technique in reconfigurable processor. It effectively reduces the reconfigure time and accelerates the multimedia applications. The processor consists of a general processor and a coarse-grained reconfigurable cell array. The technique focuses on the kernel loop body and makes sure each line of context is switched in order not interrupting the regular execution. The proposed technique is verified in FPGA verification system with the integer discrete cosine transform and the motion estimation of H.264 baseline is 3.5 times of performance increase compared with the traditional reconfigurable processor PipeRench, MorphoSys and TI DSP TMS320DM642.

Key words: reconfigurable processor, loop mapping, pipeline reconfiguration

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