Design and Verification of Efficient PLB2AXI Bus Bridge

doi:10.19678/j.issn.1000-3428.0055785

Abstract

Abstract: In order to realize the protocol conversion and efficient communication between different IP cores of the System on Chip(SoC),an efficient PLB2AXI bus bridge design scheme is proposed.By taking advantage of the bandwidth of PLB bus and AXI bus,the address,data and control signals in PLB bus protocol are converted into corresponding signals in AXI bus protocol by introducing the mechanism of pipeline transmission and read-write overlapping transmission,so as to implement the communication between two bus protocols.The functions of PLB2AXI bus bridge is verified at the module level and FPGA system level.The results show that the master cable-bridge of this scheme can converse protocol correctly,and time consuming is only 54.41% of that of the traditional master cable-bridge,so it has a higher conversion and transmission efficiency.

Key words: bus bridge, System on Chip(SoC), pipeline transmission, read-write overlaping, Field-Programmable Gate Array(FPGA)

摘要： 为实现片上系统不同IP核之间的协议转换与高效通信，提出一种高效率PLB2AXI总线桥设计方案。利用PLB与AXI高性能总线的带宽优势，通过引入流水线传输和读写重叠传输机制，将PLB总线协议中的地址、数据和控制信号转换为AXI总线协议中的相应信号，从而实现两种总线协议之间的通信。从模块级和FPGA系统级两个方面对PLB2AXI总线桥的功能进行验证，结果表明，该方案设计的总线桥能够正确转换协议，且耗时仅为传统总线桥的54.41%，具有更高的转换传输效率。

关键词: 总线桥, 片上系统, 流水线传输, 读写重叠, 现场可编程门阵列

CLC Number:

TN402

ZHANG Hao, WEI Jinghe. Design and Verification of Efficient PLB2AXI Bus Bridge[J]. Computer Engineering, 2020, 46(8): 228-234.

张浩, 魏敬和. 高效率PLB2AXI总线桥的设计与验证[J]. 计算机工程, 2020, 46(8): 228-234.

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References

[1] CAO Fan.Bridge design based on AMBA and WISHBONE bus[D].Hefei:University of Science and Technology of China,2011.(in Chinese)曹凡.基于AMBA和WISHBONE总线的桥接设计[D].合肥:中国科学技术大学,2011.
[2] DAI Jun.IP core design for motor control SoC based on AMBA bus[D].Shanghai:Shanghai Jiaotong University,2016.(in Chinese)戴骏.基于AMBA总线面向电机控制专用SoC的IP核设计[D].上海:上海交通大学,2016.
[3] IBM.128-bit processor local bus architecture specifications,version 4.4[EB/OL].[2019-07-11].https://www.mendeley.com/research/128bit-processor-local-bus-architecture-specifications.
[4] LIU Shuang.Application and verification of PCI-PLB bridge IP core in SoC[D].Xi'an:Xidian University,2013.(in Chinese)刘爽.PCI-PLB桥IP核在SOC中的应用与验证[D].西安:西安电子科技大学,2013.
[5] IBM.Processor local bus functional model toolkit,user's manual,version4.9.2/4.3[EB/OL].[2019-07-11].https://ptolemy.berkeley.edu/projects/embedded/mescal/forum/7/coreconnect_bfl.pdf.
[6] ZHANG Kaijing.Design and verification of PLB bus and related modules for system on chip[D].Xi'an:Xidian University,2013.(in Chinese)张开晶.片上系统PLB总线及其相关模块的设计与验证[D].西安:西安电子科技大学,2013.
[7] PENG Wei.Research on user IP core interface technology based on PLB bus[D].Hefei:Hefei University of Technology,2011.(in Chinese)彭维.基于PLB总线的用户IP核接口技术研究[D].合肥:合肥工业大学,2011.
[8] MATH S S,MANJULA R B.Design of AMBA AXI4 protocol for system-on-chip communication[EB/OL].[2019-07-11].http://idc-online.com/technical_references/pdfs/electronic_engineering/Design%20of%20AMBA.pdf.
[9] LAKHMANI V,ALI N,TRIPATHI V S.AXI compliant DDR3 controller[C]//Proceedings of International Conference on Computer Modeling and Simulation.Washington D.C.,USA:IEEE Press,2010:1-5.
[10] YU Zhiguo,WEI Jinghe.A collaborative environment for 32 bit SoC verification[J].Electronics and Packaging,2008,8(10):42-45.(in Chinese)虞致国,魏敬和.一种32 Bit SoC软硬件协同验证环境的实现[J].电子与封装,2008,8(10):42-45.
[11] IBM.128-bit processor local bus architecture specifications,version 4.7[EB/OL].[2019-07-11].https://www.mendeley.com/research/128bit-processor-local-bus-architecture-specifications.
[12] JIAO Longtao,GAO Xin.Design and implementation of a two-way AXI2AHB bus bridge with low power consumption and high efficiency[J].Radio Communication Technology,2017,43(2):78-82.(in Chinese)焦龙涛,高欣.一种低功耗高效率的双向AXI2AHB总线桥设计与实现[J].无线电通信技术,2017,43(2):78-82.
[13] WEI Jinghe,WU Xiaojie,YU Zhiguo.Low-power SoC design and technical implementation[J].Electronics and Packaging,2009,9(5):20-23.(in Chinese)魏敬和,吴晓洁,虞致国.SoC低功耗设计及其技术实现[J].电子与封装,2009,9(5):20-23.
[14] XIAO Fuming,LI Dongsheng,DU Gaoming,et al.Design of AXI bus based MPSoC on FPGA[C]//Proceedings of the 3rd International Conference on Anti-counterfeiting,Security,and Identification in Communication.Washington D.C.,USA:IEEE Press,2009:560-564.
[15] PU Jie,LI Guiyong.Design and implementation of DMA controller based on AXI bus[J].Journal of Chongqing University of Posts and Telecommunications(Nature Science Edition),2012,24(20):174-177.(in Chinese)蒲杰,李贵勇.基于AXI总线的DMA控制器的设计与实现[J].重庆邮电大学学报(自然科学版),2012,24(20):174-177.
[16] YANG Shunqi.Research and implementation of AMBA AXI4 bus[D].Harbin:Harbin Institute of Technology,2011.(in Chinese)杨舜琪.AMBA AXI4总线的研究与实现[D].哈尔滨:哈尔滨工业大学,2011.
[17] LI Kang,LEI Li,FAN Yong,et al.A design of the PLB to AHB bus bridge[C]//Proceedings of 2011 Inter-national Conference on Electronics,Communications and Control.Washington D.C.,USA:IEEE Press,2011:1-5.
[18] BHASKAR B J,LAKSHMINARAYANA M,CHIKKANNA M.AXI bus master interface development using Verilog[C]//Proceedings of 2011 International Conference on Embedded Electronics and Computing Systems.Washington D.C.,USA:IEEE Press,2011:1-6.
[19] Synopsys.HAPS Prototyping Solution[EB/OL].[2019-07-11].https://www.synopsys.com/verification/prototyping/haps.html.
[20] ARM.AMBA AXI and ACE protocol specification[EB/OL].[2019-07-11].http://www.arm.com.

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