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Computer Engineering ›› 2006, Vol. 32 ›› Issue (21): 1-2,21. doi: 10.3969/j.issn.1000-3428.2006.21.001

• Degree Paper •     Next Articles

Research on the Formal Semantics of Verilog Based on ASM

HU Yanxiang1,2   

  1. (1. School of Electronics and Information Engineering, Tianjin University, Tianjin 300072;
    2. School of Computer, Tianjin Normal University, Tianjin 300072)
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-11-05 Published:2006-11-05

Verilog语义的ASM表示方法研究

胡燕翔1,2   

  1. (1. 天津大学电子信息工程学院,天津 300072;2. 天津师范大学计算机学院,天津 300072)

Abstract: Verilog’s formal semantics using the abstract states machine are studied, and the formal definition of assignment statements and delay/event control mechanism is given. Comparing with Borger’s definition on VHDL, the key methods on how to translate Verilog description to VHDL are explained. In the end, the simulation differences before and after translation are studied.

Key words: Verilog formal semantics, Abstract states machine, Delay/Eevent control

摘要: 使用抽象状态机模型(ASM)对Verilog的语义进行研究,给出各类赋值语句和延迟/事件控制结构的形式定义。以此为基础与VHDL进行对比,说明各种赋值语句和延迟/事件控制结构向VHDL的转换方法以及二者在转换前后的差异。

关键词: Verilog语义, 抽象状态机, 延迟/事件控制

CLC Number: