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Computer Engineering ›› 2011, Vol. 37 ›› Issue (22): 24-27. doi: 10.3969/j.issn.1000-3428.2011.22.006

• Networks and Communications • Previous Articles     Next Articles

Research on Hierarchical Explicit Memory Access Mechanism Based on ESCA System

RAO Jin-li, WU Dan, CHEN Pan, DONG Mian, DENG Cheng-nuo, DAI Kui, ZOU Xue-cheng   

  1. (Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China)
  • Received:2011-05-10 Online:2011-11-18 Published:2011-11-20

基于ESCA系统的层次化显式访存机制研究

饶金理,吴 丹,陈 攀,董 冕,邓承诺,戴 葵,邹雪城   

  1. (华中科技大学电子科学与技术系,武汉 430074)
  • 作者简介:饶金理(1987-),男,硕士研究生,主研方向:计算机体系结构,大规模集成电路设计;吴 丹、陈 攀,博士研究生; 董 冕、邓承诺,硕士研究生;戴 葵、邹雪城,教授、博士生 导师
  • 基金资助:

    国家自然科学基金资助项目(NSFC60973035, NSFC60976027);湖北省自然科学基金资助项目(2010CBD02705)

Abstract:

To address the memory wall issue of the high performance hybrid computing systems, this paper proposes a novel hierarchical explicit memory access mechanism based on the analysis of hybrid computing mode and the limitations of the traditional memory access mechanism. The proposed mechanism is implemented and evaluated on a multi-core hybrid computing system Engineering and Scientific Computing Architecture (ESCA). Experimental results show that the hidden of memory access latency can occupy 56% of the total run time and achieve 1.5 times speedup with the kernel of DGEMM, which proves that the proposed memory access mechanism is beneficial to fill the gap between computing and memory, thus improving the system efficiency.

Key words: hybrid computing, memory wall, multi-core processor, Engineering and Scientific Computing Architecture(ESCA) system, hierarchical explicit memory access, hidden of latency

摘要:

针对高性能混合计算系统中的存储墙问题,在分析其计算模式特点及传统访存机制局限性的基础上,提出适用于混合计算系统的层次化显式存储访问机制,并基于ESCA多核处理器系统进行实现和评测。实验结果显示,针对核心应用程序DGEMM,延迟隐藏能够占据整体运行时间的56%,并获得1.5倍的加速比,能弥补计算与存储访问间的速度差异,提高系统计算效率。

关键词: 混合计算, 存储墙, 多核处理器, ESCA系统, 层次化显示存储访问, 延迟隐藏

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