Abstract: Reconfigurable systems are very efficient on computing intensive domains, and critical loops of algorithms can be set up on a reconfigurable array especially. But how to mapping applications is still a hard work which limits the development of reconfigurable technique. This paper proposes a way to define timing models and method to modify the reconfigurable mapping performance. It is meaningful to the compiler designs. Memory wall on a hardware array and data flow graph topology of algorithms are considered, and the setup/hold times of a loop mapping process is also derived. The definition of path’s timing feature gives a new way to take out a reconfigurable compiler. Verification shows 43% performance improvement is achieved on mapping critical loop deblocking of H.264 decoding to a reconfigurable system.

Key words: critical loop, reconfigurable array, algorithm mapping, timing model, array setup time, array hold time

摘要： 通过定义算法关键循环到可重构阵列映射的建立时间、保持时间等核心时序参数，分析存储器带宽有限、算法数据流图拓扑不规则等实际问题，给出配置时序模型的优化算法，提出路径特征等参数的描述形式，为可重构自动编译提供新的处理方式。验证结果表明，在视频算法H.264关键循环deblocking的映射过程中，该优化映射方法使得性能在原有基础上提升43%。

关键词: 关键循环, 可重构阵列, 算法映射, 时序模型, 阵列建立时间, 阵列保持时间

CLC Number: 

• TP301.6