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Design of AXI4 Master Conversion Interface Supporting Pipeline Transmission

YI Qingming,ZENG Jielin,SHI Min   

  1. (College of Information Science and Technology,Jinan University,Guangzhou 510632,China)
  • Received:2015-02-11 Online:2016-04-15 Published:2016-04-15

支持流水传输的AXI4主机转换接口设计

易清明,曾杰麟,石敏   

  1. (暨南大学信息科学技术学院,广州 510632)
  • 作者简介:易清明(1965-),女,教授、博士,主研方向为通信信号处理、ASIC设计;曾杰麟,硕士;石敏,副教授、博士。
  • 基金资助:
    广东省工程技术研究中心基金资助项目(2012gczxA003);广东省省级科技计划基金资助项目“多媒体信号处理及SoC芯片设计技术创新平台”(2013B090800022)。

Abstract: Considering the existing Advanced eXtensible Interface 4(AXI4) master interface can only work in half-duplex mode and can not apply for multiple transmissions simultaneously,a design scheme of AXI4 master conversion interface supporting pipeline transmission is proposed in this paper.By adding an address information storage module which allows the conversion interface to store the new apply transmission requests before current transmission ends,it gives out the address data on the bus until it is allowed.This scheme bases on separated state machines of reading and writing,it supports full-duplex operation and pipeline transmission.Simulation result shows that,when the host requests for two times of a 4-data continuous read and an 8-data continuous write transmission,compared with the interface supporting half-duplex mode,the interface designed by proposed scheme can save 16 clock cycles.The conversion interface can reduce the transmission cost effectively and ensure the accuracy of data transmission.

Key words: Advanced eXtensible Interface 4(AXI4) bus protocol, conversion interface, pipeline transmission, full-duplex, on-chip bus, System on Chip(SoC)

摘要: 针对现有的AXI4主机转换接口只能工作在半双工模式且不能同时发起多次传输申请的问题,提出一种支持流水传输的AXI4主机转换接口设计方案。加入地址信息存储模块,允许转换接口在主机当前传输操作未结束时对新申请的地址信息进行存储,并于总线允许发送下一个地址数据时把存储模块中的地址信息发送到总线上,同时采用读写分离的状态机进行设计,使转换接口全双工工作且支持流水传输。仿真结果表明,当主机需要进行2次4个数据的连续读传输及1次8个数据的连续写传输时,该方案设计的转换接口比半双工转换接口节省16个时钟周期,能有效减少传输耗费时间,保证数据传输的正确性。

关键词: AXI4总线协议, 转换接口, 流水传输, 全双工, 片上总线, 片上系统

CLC Number: