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Design and Implementation of H.264 Parallel Decoder Based on CUDA

CHEN Yong,WU Xiaomin,YANG Jian,XI Hongsheng   

  1. (Department of Automation,University of Science and Technology of China,Hefei 230027,China)
  • Received:2015-04-10 Online:2016-05-15 Published:2016-05-13

基于CUDA的H.264并行解码器设计与实现

陈勇,吴晓民,杨坚,奚宏生   

  1. (中国科学技术大学自动化系,合肥 230027)
  • 作者简介:陈勇(1989-),男,硕士研究生,主研方向为视频编/解码、实时视频传输与质量优化;吴晓民,博士研究生;杨坚,副教授、博士生导师;奚宏生,教授、博士生导师。
  • 基金资助:
    国家自然科学基金资助重点项目“三网融合业务接入系统的分析、建模与调控”(61233003);国家自然科学面上基金资助项目“基于在线测量的网络化媒体服务系统自适应优化与控制”(61174062)。

Abstract: Aiming at the defects of H.264 such as high complexity and large amounts of computation,this paper designs and implements the CPU+GPU heterogeneous parallel H.264 decoder based on Compute Unified Device Architecture(CUDA),which makes full use of GPU’s parallel computing ability and CPU’s logic control advantages,to improve the running speed and decoding performance.Experimental result shows that the performance is improved 2~7 times when using GPU acceleration,and the each parallel module can also accelerate 5 to 11 times,compared with that of the traditional serial decoder in FFmpeg.

Key words: Graphics Processing Unit(GPU), Compute Unified Device Architecture(CUDA), H.264 standard, video codec, parallelization

摘要: 针对H.264视频编解码标准复杂度高、运算量大的缺点,基于统一计算设备架构平台设计并实现CPU+GPU异构并行H.264解码器,利用GPU的并行计算能力和CPU的逻辑控制优势加快运行速度,提高解码性能。实验结果表明,与FFmpege中传统的串行解码器相比,利用GPU加速的H.264并行解码器能获得2倍~7倍的性能提升,各并行单独模块也可实现5倍~11倍的加速。

关键词: 图形处理器, 统一计算设备架构平台, H.264标准, 视频编解码器, 并行化

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