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Author Login Editor-in-Chief Peer Review Editor Work Office Work
Author Login Editor-in-Chief Peer Review Editor Work Office Work
Parallel Timing-driven Placement Algorithm for FPGA
ZHANG Jiaqi,SHEN Jianliang,ZHU Ke
Computer Engineering . 2017, (2): 98 -104 .  DOI: 10.3969/j.issn.1000-3428.2017.02.017

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