Abstract: In order to improve the support of the underlying image library on the Feiteng domestic DSP platform, the performance gap between the indentation and mainstream acceleration devices in the image processing field is reduced. In view of the large amount of time overhead in the Canny edge detection calculation process in image processing, a parallel algorithm for Canny gradient calculation based on FT-M7002 is proposed. First, based on the Feiteng architecture and modern parallel program optimization strategies, the algorithm is analyzed and data-level parallelism is explored, and the program is rewritten using manual SIMD vectorization to make full use of the 512-bit long SIMD computing component of the Feiteng DSP platform. Secondly, combined with the unique vector memory hierarchical structure characteristics of the platform, the memory access mode in the algorithm is analyzed. The address is offset by the first address to deal with discontinuous memory access, and the calculation and DMA are completed by means of "ping-pong" buffering. The latency of memory access is hidden. Based on the FT-M7002 experimental platform, the results show that, with the same accuracy as the original algorithm, Canny gradient parallel algorithm in the commonly used 3*3, 5*5, 7*7 core gradient calculation part of the average speed increased by 2.0, 2.5, 2.8 times respectively, the overall operating speed increased by 1.49-2.11 times.