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计算机工程 ›› 2022, Vol. 48 ›› Issue (9): 139-145. doi: 10.19678/j.issn.1000-3428.0062745

• 体系结构与软件技术 • 上一篇    下一篇

一种嵌入式硬件辅助调试机制研究与实现

刘鹏, 刘杰, 贾讯   

  1. 江南计算技术研究所, 江苏 无锡 214215
  • 收稿日期:2021-09-22 修回日期:2021-11-17 发布日期:2021-11-26
  • 作者简介:刘鹏(1982—),男,工程师、硕士,主研方向为集成电路设计;刘杰,副研究员、博士;贾迅,助理研究员、博士。
  • 基金资助:
    国家自然科学基金(61732018)。

Research and Implementation of an Embedded Hardware-Assisted Debugging Mechanism

LIU Peng, LIU Jie, JIA Xun   

  1. Jiangnan Institute of Computer Technology, Wuxi, Jiangsu 214215, China
  • Received:2021-09-22 Revised:2021-11-17 Published:2021-11-26

摘要: 某自主指令架构系列芯片(简称为GCXP)主要使用基于扫描链重用的硬件调试机制,与主流商用嵌入式芯片产品相比,该硬件调制机制安全性较低且不具备用户交互、程序下载等功能,同时缺乏嵌入式调试软件生态,不利于嵌入式产品的推广与应用。参考ARM CoreSight、RISCV Debug SPEC及SiFive开源芯片Debug Module的实现细节,结合GCXP特权架构,提出一种软硬件协同的调试中断陷入机制。使用自主特权架构中的特权程序替代部分调试中断硬件逻辑,使得在调试模块设计时无需进行CPU协同修改以及操作系统软件接口和上位机调试软件的二次开发,从而避免CPU硬件逻辑修改后大量的验证工作,同时无缝兼容历史CPU IP。分析结果表明,该中断陷入机制与RISCV Debug SPEC协议能够实现良好的协同,可以与SiFive参考开源调试模块协同工作,支持主流交互式调试软件及硬件工具,且调试模块的代码及功能覆盖率都能达到100%,可以满足流片需求。

关键词: 嵌入式调试, 开源片上调试器, 自主指令集SoC, 前端设计, 国产芯片

Abstract: A series of independent instruction architecture chips(called GCXP in this paper) mainly use the hardware debugging mechanism based on scan chain reuse.Compared to mainstream commercial embedded chip products, the hardware modulation mechanism of independent instruction architecture chips has lower security and does not exhibit user interaction, program download, and other functions.In addition, it lacks embedded debugging software ecology, which is unconducive for promoting and applying embedded products.This paper proposes a debugging interrupt trapping mechanism of software and hardware cooperation based on the implementation details of ARM CoreSight, RISCV Debug SPEC, and SiFive open-source chip Debug Module, combined with GCXP privilege architecture.The privileged program in the independent privileged architecture is used to replace a part of the debugging interrupt hardware logic so that it will not be necessary to perform Central Processing Unit(CPU) collaborative modification and secondary development of the operating system software interface and the upper computer debugging software during the debugging module design.This reduces verification work after modifying the CPU hardware logic, and it is seamlessly compatible with the historical CPU Internet Protocol(IP).The analysis results show that the interrupt trapping mechanism can cooperate reasonably with the RISCV Debug SPEC protocol, work with the SiFive reference open-source debugging module, and support mainstream interactive debugging software and hardware tools.The code and function coverages of the debugging module can reach 100%, satisfying streaming requirements.

Key words: embedded debugging, open on-chip debugger, autonomous instruction set SoC, front-end design, domestic chip

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