计算机工程 ›› 2008, Vol. 34 ›› Issue (4): 247-249.doi: 10.3969/j.issn.1000-3428.2008.04.088

• 工程应用技术实现 • 上一篇    下一篇

片上多处理器中的Cache压缩和接口压缩

肖俊华1,2,冯子军1,2,章隆兵1   

  1. (1. 中国科学院计算技术研究所,北京100080;2. 中国科学院研究生院,北京100039)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2008-02-20 发布日期:2008-02-20

Cache Compression and Interface Compression in Chip Multiprocessor

XIAO Jun-hua1,2, FENG Zi-jun1,2, ZHANG Long-bing1   

  1. (1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080;2. School of Graduate, Chinese Academy of Sciences, Beijing 100039)
  • Received:1900-01-01 Revised:1900-01-01 Online:2008-02-20 Published:2008-02-20

摘要: 提出一种简单的基于频繁值和频繁模式的压缩方法,给出结合Cache压缩技术和接口压缩技术的片上多处理器结构。全系统的模拟结果表明Cache压缩技术和接口压缩技术能提高片上多处理器中Cache的有效容量和pin的有效带宽,从而提高系统的性能。实验表明只采用Cache压缩技术平均能提高10%的性能,只采用接口压缩技术平均能提高5.5%的性能,同时采用Cache压缩技术和接口压缩技术平均能提高12%的性能。

关键词: 片上多处理器, Cache压缩, 接口压缩

Abstract: This paper proposes a simple frequent value and frequent pattern based compression method, and a chip-multiprocessor design combining cache compression and interface compression techniques. The full system simulation shows that Cache compression and interface compression techniques can increase the effective Cache capacity and effective pin bandwidth, and then improve the performance of system. Experimental results show that only using cache compression can improve performance by 10%, only using interface compression can improve performance by 5.5%, combining cache compression and link compression techniques can improve performance by 12%.

Key words: chip multiprocessor, cache compression, interface compression

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