计算机工程 ›› 2009, Vol. 35 ›› Issue (10): 229-231.doi: 10.3969/j.issn.1000-3428.2009.10.076

• 工程应用技术与实现 • 上一篇    下一篇

应用于网络安全协处理器的真随机数产生器

张晓峰,白国强,陈弘毅   

  1. (清华大学微电子学研究所,北京 100084)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-05-20 发布日期:2009-05-20

True Random Number Generator for Network Security Co-processor

ZHANG Xiao-feng, BAI Guo-qiang, CHEN Hong-yi   

  1. (Institute of Microelectronics, Tsinghua University, Beijing 100084)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-05-20 Published:2009-05-20

摘要: 介绍一款基于环形振荡器的真随机数产生器。电路使用固定频率时钟采样可控频率振荡器的输出,使用级间反馈随机改变可控频率振荡器的振荡频率。设计启动电路来保证环形振荡器快速起振,在使能信号无效时断开振荡电路以节省功耗。电路采用CMOS 0.18 μm标准工艺实现,使用Hspice_RF仿真环形振荡电路的相位抖动以获得最优设计参数。仿真结果表明,电路在输出速率为1 Gb/s时产生的随机序列具有良好的随机性,该设计可用于网络安全协处理器中。

关键词: 网络安全协处理器, 真随机数产生器, 环形振荡器, 启动电路

Abstract: This paper introduces a ring oscillator based True Random Number Generator(TRNG) for network security co-processor. To obtain better randomicity, the circuit utilizes a fixed frequency clock to sample the output of a frequency variable high speed ring oscillator. Inter-stage feedback ring is introduced to control the frequency of the high speed ring oscillator to accumulate the phase noise. Start-up circuit is designed not only to make the ring oscillator much easier to oscillate, but also to reduce the power dissipation by introducing enable signal. TRNG is designed under CMOS 0.18 μm standard process. Hspice_RF is used to perform jitter simulation to acquire optimum parameters. Simulation results show that random bit stream can pass statistical test for randomness under 1 Gb/s sampling frequency.

Key words: network security co-processor, True Random Number Generator(TRNG), ring oscillator, start-up circuit

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