计算机工程 ›› 2011, Vol. 37 ›› Issue (24): 236-238.doi: 10.3969/j.issn.1000-3428.2011.24.079

• 工程应用技术与实现 • 上一篇    下一篇

多路有序优先级和有序环形仲裁器设计

杨冬勤 1,黄 航 1,张小燕 2,于忠臣 1   

  1. (1. 北京工业大学北京市嵌入式系统重点实验室,北京 100124; 2. 北京航空航天大学化学与环境学院,北京 100191)
  • 收稿日期:2011-06-28 出版日期:2011-12-20 发布日期:2011-12-20
  • 作者简介:杨冬勤(1986-),男,硕士研究生,主研方向:数字电路设计;黄 航、张小燕,硕士研究生;于忠臣,教授、博士生导师

Design of N-way Ordered Priority and Ordered Ring Arbiter

YANG Dong-qin 1, HUANG Hang 1 , ZHANG Xiao-yan 2, YU Zhong-chen 1   

  1. (1. Embedded System Key Lab of Beijing, Beijing University of Technology, Beijing 100124, China; 2. School of Chemistry and Environment, Beihang University, Beijing 100191, China)
  • Received:2011-06-28 Online:2011-12-20 Published:2011-12-20

摘要: 为解决传统仲裁器不能记忆请求顺序的问题,设计多路有序优先级仲裁器和有序环形仲裁器。通过先入先出(FIFO)电路来保存请求的先后顺序,将FIFO电路分别与优先级仲裁器和环形仲裁器组合,从而构成有序仲裁器。实验结果表明,该设计能简化复杂度,提高仲裁器处理请求能力,但延时和面积性能略有下降。

关键词: 有序仲裁器, 优先级仲裁器, 环形仲裁器, 先入先出电路, 令牌

Abstract: To improve shortcoming of traditional arbiters, this paper proposes N-way ordered arbiter, which is based on combination of First In First Out(FIFO) and priority arbiter and ring arbiter respectively. FIFO is used for savingthe request orders. It proposes a new structure of priority and a new ring arbiter. Results show that, modular design simplifies the complexity, improves the ability of arbiter to process the request, and the ability of saving the request in order reduces latency and area properties.

Key words: ordered arbiter, priority arbiter, ring arbiter, First In First Out(FIFO) circuit, token

中图分类号: