计算机工程 ›› 2012, Vol. 38 ›› Issue (9): 271-274.doi: 10.3969/j.issn.1000-3428.2012.09.083

• 开发研究与设计技术 • 上一篇    下一篇

面向固件代码分析的虚拟指令集体系结构设计

赵 远,曾光裕,王 炜,崔 晨,高洪博   

  1. (解放军信息工程大学信息工程学院,郑州 450002)
  • 收稿日期:2012-01-06 出版日期:2012-05-05 发布日期:2012-05-05
  • 作者简介:赵 远(1984-),男,硕士研究生,主研方向:信息安 全;曾光裕,副教授;王 炜,讲师、博士;崔 晨,硕士研究生;高洪博,博士研究生
  • 基金项目:
    国家“863”计划基金资助项目(2009AA01Z434)

Design of Virtual Instruction Set Architecture for Firmware Code Analysis

ZHAO Yuan, ZENG Guang-yu, WANG Wei, CUI Chen, GAO Hong-bo   

  1. (Institute of Information Engineering, PLA Information Engineering University, Zhengzhou 450002, China)
  • Received:2012-01-06 Online:2012-05-05 Published:2012-05-05

摘要: 传统虚拟指令集体系结构不能同时满足简单性和高效性的要求。为此,提出一种面向固件代码分析的虚拟指令集体系结构构造方法。设计多目标固件代码分析平台,在可配置虚拟硬件结构的基础上,获取最小完备指令集,并说明扩展虚拟指令集的方法。实验结果表明,该方法能降低翻译代码膨胀率,目标指令模拟时间比传统方法减少19%~35%。

关键词: 固件代码, 虚拟指令集体系结构, 翻译代码膨胀率, 最小完备指令集, 虚拟硬件

Abstract: For traditional Virtual Instruction Set Architecture(V-ISA) can not satisfy both brevity and high-efficiency well, this paper proposes a Virtual Instruction Set Architecture(V-ISA) design method for firmware code analysis. A muti-target firmware code analysis platform is designed, and on the basis of virtual hardware configuration that can be configured, a method for developing virtual instruction set is proposed that it first build the minimal complete instruction set and then expands it. Experimental result shows that this method can reduce translated-code expansion rate and get the simulation costs have a reduction of 19%~35% compared with the conventional one.

Key words: firmware code, Virtual Instruction Set Architecture(V-ISA), translated-code expansion rate, minimal complete instruction set, virtual hardware

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