摘要： 在传统MD5算法中，最影响执行速度的步骤是对关键路径变量B的求取。为提高算法的执行速度，对关键路径进行优化，将加法运算分成两步，由此缩短B的求取时间。用Verilog语言描述改进算法的硬件结构，并对其进行综合。实验结果表明，该电路的面积为85 678 μm2、频率为142.8 MHz，与传统算法相比，改进算法的执行速度提高了1.989倍。
Abstract: How to calculate the value of B in the critical path is the most key factor which affects the execution speed of traditional MD5 algorithm. In order to improve execution speed, this paper optimizes the critical path, and separates the add calculation to two steps to shorten the time of calculating value of B. Verilog Hardware Description Language(HDL) is adopted to describe the circuit structure and DC is used to get area and frequency data. Experimental result shows that execution frequency is 142.8 MHz and area is 85 678 μm2, and the improved algorithm’s speed is 1.989 times compared with traditional algorithm.
Verilog Hardware Description Language(HDL),