参考文献
[1] 王育红, 薛筱明, 樊昌信. 一种全数字接收机结构[J]. 西安电子科技大学学报, 1998, 25(3): 374-378.
[2] Gardner F M. A BPSK/QPSK Timing-error Detector for Sampled Receivers[J]. IEEE Trans. on Communications, 1986, 34(3): 423-429.
[3] Mueller K H, Muller M. Timing Recovery in Digital Synch- ronous Data Receivers[J]. IEEE Trans. on Communications, 1976, 24(5): 516-530.
[4] Andrea A N D, Luise M. Design and Analysis of a Jitter-free Clock Recovery Scheme for QAM Systems[J]. IEEE Trans. on Communications, 1993, 41(9): 1296-1299.
[5] Ogmundson P G, Driessen P F. Zero-crossing DPLL Bit Syn- chronizer with Pattern Jitter Compensation[J]. IEEE Trans. on Communications, 1991, 39(4): 603-612.
[6] Lin Dongmin. A Modified Gardner Detector for Symbol Timing Recovery of M-PSK Signals[J]. IEEE Trans. on Communications, 2004, 52(10): 1643-1647.
[7] Yang Dewei, Yan Chaoxing, Wang Hua, et al. Extension to Gardner Timing Error Detector for QPSK Signals[C]//Proc. of International Conference on Wireless Communications and Signal Processing. [S. l.]: IEEE Press, 2010: 1-5.
[8] Gardner F M. Interpolation in Digital Modems-Part I: Fun- damentals[J]. IEEE Trans. on Communications, 1993, 41(3): 501-507.
[9] Erup L, Gardner F M. Interpolation in Digital Modems-Part II: Implementation and Performance[J]. IEEE Trans. on Communications, 1993, 41(6): 998-1008.
[10] Farrow C W. A Continuously Variable Digital Delay Ele- ment[C]//Proc. of IEEE International Symposium on Circuits and Systems. [S. l.]: IEEE Press, 1988: 2641-2645.
[11] Shayan Y R. All Digital Phase-locked Loop: Concepts, Design and Applications[J]. IEE Proceedings of Radar and Signal Processing, 1989, 136(1): 53-56.
编辑 顾逸斐
|