摘要： 片上多核处理器已逐渐取代传统超标量处理器成为集成电路设计的主流结构,但芯片的存储墙问题依旧是设计的一个难题。CMP通过大容量的末级高速缓存来缓解访存压力。在软件编程模式向多线程并行方式转变的背景下,针对多线程应用在多核处理器上的Cache访问特征,提出一种面向私有末级Cache的优化算法,通过硬件缓冲器记录处理器访存地址,从而实现共享数据在Cache间的传递机制,有效降低Cache失效开销。实验结果表明,在硬件开销不超过Cache部件0.1%的情况下,测试用例平均加速比为1.13。

关键词: 片上多核处理器, 存储墙, 末级Cache, 失效开销, 缓冲器

Abstract: The design of processors changes from traditional superscalar ones to Chip Multi-processors(CMP).CMP becomes the mainstream of computer architecture.But the memory wall problem is still one of the design challenges.With the help of large volume last level Cache,CMP succeeds to relieve memory pressure.The pattern of software programming changes toward the parallel mode.This paper presents an algorithm about Last Level Cache(LLC) optimization on CMP,based on characteristic of Cache access.By the use of the hardware buffer recording processors’ access address,the algorithm enables the transfer mechanism of shared data between Caches,and reduces Cache miss penalty effectively.Experimental results show that,average speedup of test is 1.13 when the cost of hardware is less than 0.1% of Cache.

Key words: Chip Multi-processors(CMP), memory wall, Last Level Cache(LLC), failure overhead, buffer

中图分类号: 

• TP303