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计算机工程 ›› 2010, Vol. 36 ›› Issue (21): 283-285. doi: 10.3969/j.issn.1000-3428.2010.21.102

• 开发研究与设计技术 • 上一篇    下一篇

CMP中基于目录的协作Cache设计方案

赵小雨1,2,吴俊敏1,2,隋秀峰1,2,王庆波3,唐轶轩1,2   

  1. (1. 中国科学技术大学计算机科学与技术学院,合肥 230027;2. 中国科学技术大学苏州研究院,江苏 苏州 215123; 3. IBM中国研究院,北京 100094)
  • 出版日期:2010-11-05 发布日期:2010-11-03
  • 作者简介:赵小雨(1983-),男,硕士研究生,主研方向:多核处理器;吴俊敏,副教授、博士;隋秀峰,博士研究生;王庆波,硕士;唐轶轩,博士研究生
  • 基金资助:
    国家“863”计划基金资助项目(2008AA01Z111);IBM大学合作联合研究基金资助项目(JSA200906010);中国科学技术大学研究生创新基金资助项目(KD2008059)

Design Scheme of Directory-based Cooperative Cache in CMP

ZHAO Xiao-yu1,2 , WU Jun-min1,2, SUI Xiu-feng1,2, WANG Qing-bo3, TANG Yi-xuan1,2   

  1. (1. School of Computer Science and Technology, University of Science and Technology of China, Hefei 230027, China; 2. Suzhou Institute for Advanced Study, University of Science and Technology of China, Suzhou 215123, China; 3. IBM Research-China, Beijing 100094, China)
  • Online:2010-11-05 Published:2010-11-03

摘要: 片上多处理器中二级Cache的设计和管理是影响其性能的关键因素之一。在私有二级Cache的基础上,提出一种基于集中式一致性目录的协作Cache设计方案,通过有效地管理片上存储资源来优化处理器的性能,从而使该协作Cache具有平均访存延迟小、Cache缺失率低、可扩展性好等优点。实验结果显示,与共享二级Cache设计相比,协作Cache可以将4核处理器的吞吐量平均提高13.5%,而其硬件开销约为8.1%。

关键词: 协作Cache, 集中式一致性目录, 片上多处理器, 流感知

Abstract: One of the key factors that affects the performance of Chip MultiProcessors(CMP) is the design and management of L2 cache. This paper proposes the design method of cooperative caching using central coherence directory hardware based on private L2 cache, which can manage on-chip storage resources more efficiently to improve the performance of CMP. This cooperative caching combines the lower average memory access latency of private cache and the lower miss rate of shared cache, it also has strong scalability. Experimental result shows that on the average, the cooperative caching increases the IPC by 13.5%, compared with shared L2 cache, and the hardware overhead is about 8.1%.

Key words: cooperative cache, central coherence directory, Chip MultiProcessors(CMP), stream aware

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