Abstract:

Heterogeneous multi-core processors have become the mainstream solution for current computer platforms owing to their high performance, low power consumption, and wide range of application scenarios. In addition, the large-capacity Static Non-Uniform Cache Architecture(S-NUCA) has a low average access time. However, the rising transistor size results in challenges to the resource scheduling and power control of heterogeneous multi-core processors. Traditional scheduling algorithms ignore the cache access latency between cores despite S-NUCA-based multi-core processors, and traditional thermal management schemes only provide chip-level power constraints, which easily degrade the system performance owing to low core utilization. In this study, we propose Thermal Security Constrained Dynamic Mapping(TSCDM), a dynamic thread scheduling mechanism for S-NUCA heterogeneous multi-core systems that satisfies thermal security constraints. TSCDM utilizes a phase detection technique based on dynamic Instructions Per Clock(IPC) values. It predicts the IPC values of threads based on Artificial Neural Network(ANN) to obtain the optimal binding relationship between threads and core types and obtain optimal mapping and task migration policies based on task classification according to S-NUCA cache characteristics. Finally, TSCDM allocates power budgets for each core in real time based on the on-chip thermal model. The results of running the SPLASH-2 performance test suite on HotSniper demonstrate that TSCDM achieves advantages in both speedup ratio and resource utilization compared to traditional scheduling schemes and other machine learning-based scheduling schemes. Moreover, the employed Transient-Temperature Based Safe Power(T-TSP)algorithm further reduces the core thermal headroom than the traditional Thermal Safe Power(TSP) algorithm, while the processor has a higher energy efficiency ratio across the full frequency band.

Key words: heterogeneous multi-core processor, Artificial Neural Network(ANN), thread scheduling, phase detection, Thermal Safe Power(TSP)

摘要：

异构多核处理器凭借其高性能、低功耗和广泛的应用场景而成为当前计算机平台的主流方案，且大容量的非均匀缓存架构（S-NUCA）具有较低的平均访问时间。然而，不断上升的晶体管规模给异构多核处理器的资源调度和功耗控制带来挑战，传统的调度算法在面对基于S-NUCA的多核处理器时忽略了核心之间的缓存访问延迟，且传统热管理方案只提供芯片级功率约束，容易使得系统因核心使用率降低而造成性能下降。为此，提出一种适用于S-NUCA异构多核系统、满足热安全约束的动态线程调度机制TSCDM。利用基于动态每周期指令（IPC）值的阶段检测技术，并基于人工神经网络预测线程的IPC值，以获取线程与核心类型的最佳绑定关系，依据S-NUCA缓存特性获得最优映射和基于任务分类的任务迁移策略。在此基础上，TSCDM基于片上热模型为每个核心实时分配功率预算。在HotSniper上运行SPLASH-2性能测试套件进行实验，结果表明，相较于传统调度方案与基于机器学习的调度方案，TSCDM在加速比和资源利用率上均表现出优势，TSCDM中使用的基于瞬态温度的安全功率算法相比传统热安全功率算法能够降低核心热余量，同时处理器的全频段均有更高的能效比。

关键词: 异构多核处理器, 人工神经网络, 线程调度, 阶段检测, 热安全功率