Abstract: In recent years, power consumption along with silicon area has become the key factor in the chip design, especially in the digital signal process block. Most of digital signal process block are designed in standard cell. One way of low power design based on standard cell is using minimum-sized device. This paper presents a low-power scheme for the VLSI implementation of finite-impulse response (FIR) filters based on standard cell. The scheme is a cross level solution in the view of design flow. A multi-hierarchy pipeline scheme is in the architecture level, integrating addition into Wallace_Tree is used in logic level, which guarantees achieving minimum-sized device solution in circuit level. Simulation shows that 20% of the power is saved with the proposed scheme, which is flexible and can be applied to other similar designs.

Key words: Low-power, Digital signal process, FIR filter, IC, MAC

摘要： 功耗与硅面积一样已成为芯片设计中的关键问题，尤其是在数字信号处理集成电路设计中。基于标准单元的VLSI设计是实现数字信号处理模块芯片或模块的重要方法。该文提出了一种基于标准单元的低功耗FIR滤波器多层次设计方案，其中体系结构层次采用多层流水线策略，逻辑层次将加法集成到部分积压缩中，在电路层次采用最小器件，从而在最大限度减少面积的同时降低了FIR的功耗。根据实际需求，该设计方案易于扩展和变换，可灵活应用到其它类似的滤波器设计中。实现结果表明在TSMC0.25标准单元库下FIR的功耗最多可降低20％以上。

关键词: 低功耗, 数字信号处理, FIR滤波器, 集成电路, 乘累加器