ATPG for Digital Circuits with Memory Chips

doi:10.3969/j.issn.1000-3428.2007.23.088

Computer Engineering ›› 2007, Vol. 33 ›› Issue (23): 252-254,. doi: 10.3969/j.issn.1000-3428.2007.23.088

• Engineer Application Technology and Realization • Previous Articles Next Articles

ATPG for Digital Circuits with Memory Chips

CHENG Ben-mao, YANG Shi-yuan, WANG Hong, JU Yan-qiu

(Automation Department, Tsinghua University, Beijing 100084)

Received:1900-01-01 Revised:1900-01-01 Online:2007-12-05 Published:2007-12-05

含存储器数字电路系统的自动测试生成

成本茂，杨士元，王红，鞠艳秋

（清华大学自动化系，北京 100084）

Abstract

Abstract: Two new structural models of ROM and RAM for testing are given, which can be used as testing primitives in the digital automatic test pattern generation(ATPG) systems. Test patterns for circuits with ROM chips are generated automatically after ROM’s converting to a combinational model, while the ATPG problems for circuits with RAM chips are also resolved after RAM is equivalent to a sequential model.

Key words: memory, structual model, automatic test pattern generation(ATPG), fault simulation

摘要： 已有的数字电路自动测试生成(ATPG)软件没有存储器的结构模型，不支持对存储器电路的自动测试生成。该文分析了2类存储器的功能特征，提出了面向测试的ROM和RAM结构模型的建立方法，其中，ROM根据所储存的数据等效成组合电路模型， RAM利用新建立的RAMBIT基元等效成利于测试的时序电路模型。将其应用于ATPG软件中，解决了含存储器数字电路的自动测试生成问题。

关键词: 存储器, 结构模型, 自动测试生成, 故障仿真

CLC Number:

N945.12

CHENG Ben-mao; YANG Shi-yuan; WANG Hong; JU Yan-qiu. ATPG for Digital Circuits with Memory Chips[J]. Computer Engineering, 2007, 33(23): 252-254,.

成本茂;杨士元;王红;鞠艳秋.

含存储器数字电路系统的自动测试生成

[J]. 计算机工程, 2007, 33(23): 252-254,.

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