Abstract: A multiplier module in Elliptic Curve Cryptosystem(ECC) and Hyper-Elliptic Curve Cryptosystem(HECC) is introduced. On the basis of three existed multiplier algorithms, the hardware configuration is designed and implemented by using VHDL. Moreover, the speed of implementation and the chip area are compared separately. Experimental results show the 8 bit parallel mixed multiplier has better performance than other multipliers.

Key words: Field Programmable Gate Array(FPGA), Elliptic Curve Cryptosystem(ECC), Hyper-Elliptic Curve Cryptosystem(HECC)

摘要： 介绍椭圆曲线密码系统和超椭圆曲线密码系统中的乘法模块，在现有的3种乘法算法基础上，设计乘法的硬件框图，并用VHDL语言加以实现，同时对其实现速度和芯片面积进行比较。实验结果表明，在4个不同乘法器的实现方案中，8 bit串并混合乘法器的整体性能较优。

关键词: 现场可编程门阵列, 椭圆曲线密码系统, 超椭圆曲线密码系统

CLC Number: 

• TP309.7