[1] |
HUANG Zhengwei, LIU Hongwei, XU Yuan.
Design of Ultra-Low-Power RISC-V Dedicated Processor for IToF Sensor
[J]. Computer Engineering, 2022, 48(9): 146-154.
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[2] |
FENG Yifei, DING Nan, YE Junchao, CHAI Zhilei.
Design and Implementation of Domain-Specific Low-Latency and High-Bandwidth TCP/IP Offload Engine
[J]. Computer Engineering, 2022, 48(9): 162-170.
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[3] |
XI Zhiwen, CAI Jingjing, YANG Wenmin, CHAI Zhilei.
Concurrent Request Scheduling Mechanism for FPGA Cloud Platform Based on Microservice Architecture
[J]. Computer Engineering, 2022, 48(7): 206-213.
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[4] |
GONG Jie, ZHAO Shuo, HE Hu, DENG Ning.
Design of Quantized CNN Acceleration System Based on FPGA
[J]. Computer Engineering, 2022, 48(3): 170-174,196.
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[5] |
HUANG Rui, JIN Guanghao, LI Lei, JIANG Wenchao, SONG Qingzeng.
Design and Implementation of Accelerator for Lightweight Neural Network
[J]. Computer Engineering, 2021, 47(9): 185-190,196.
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[6] |
ZHAO Chenyuan, LI Wenxin, ZHANG Qingxi.
An Improved Real-Time Semi-Global Stereo Matching Algorithm and Its Hardware Implementation
[J]. Computer Engineering, 2021, 47(9): 162-170.
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[7] |
YUAN Jiawei, SONG Qingzeng, WANG Xuechun, JIANG Wenchao, JIN Guanghao.
Performance and Power Consumption Measurement and Analysis of Edge Computing Devices
[J]. Computer Engineering, 2021, 47(2): 233-238,245.
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[8] |
SHI Yongquan, JING Naifeng.
Evaluation Method Based on FPGA Emulation for Resistive Neural Network Accelerators
[J]. Computer Engineering, 2021, 47(12): 209-214.
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[9] |
WU Jianfeng, ZHENG Bowen, NIE Yi, CHAI Zhilei.
FPGA Accelerator for 3DES Algorithm Based on OpenCL
[J]. Computer Engineering, 2021, 47(12): 147-155,162.
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[10] |
SONG An, WANG Qin, GU Dawu, GUO Zheng, LIU Junrong, ZHANG Chi.
FPGA-based Collection Method for Power Information of Clock Synchronization
[J]. Computer Engineering, 2020, 46(6): 115-121.
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[11] |
LI Tao, HAN Peng, HOU Guandong, ZHAN Jiayuan.
Design and Implementation of ORUDP Protocol Stack Based on FPGA
[J]. Computer Engineering, 2020, 46(6): 155-163.
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[12] |
KONG Feiyue, JIANG Xueqin, WAN Xuefen, CHEN Sijing, CUI Jian, YANG Yi.
Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder
[J]. Computer Engineering, 2020, 46(5): 207-215.
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[13] |
YANG Fengfan, CHANG Jinfan, WANG Zheng.
A Data Transmission Method for High Precision of Time Synchronization
[J]. Computer Engineering, 2020, 46(2): 118-125,133.
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[14] |
LI Chao, LI Bo, DING Hongwei, YANG Zhijun, LIU Qianlin.
Design and Implementation of Tactical Data Link Protocol Based on FPGA
[J]. Computer Engineering, 2020, 46(10): 173-181.
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[15] |
LI Kang, ZHANG Lufei, ZHANG Xinwei, YU Gongjian, LIU Jiahang, WU Dong, CHAI Zhilei.
Design of Spiking Neural Network Simulator Based on FPGA Cluster
[J]. Computer Engineering, 2020, 46(10): 201-209.
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