Abstract: This paper proposes an IP core design, aiming at the problem of randomized jitter and large error in pure software design of traditional Precision Time Protocol(PTP). It gives prominence to adopt digital logic circuit to achieve getting of precision time stamp, synchronization algorithm and quartz oscillator frequency-compensated algorithm and state-transfer controlled algorithm, makes use of oscillator’s divided frequency adjusted to reduce influence of oscillator’s frequency-excursion and circumstance factor to precision and stability of synchronization. Simulation result shows that this design has higher synchronization precision, and precision value can reach 10 ns.

Key words: Precision Time Protocol(PTP), IP core, synchronization, state transfer control

摘要： 针对传统精确时间协议的软件设计中存在随机抖动、误差大的问题，提出一种IP核设计。该设计采用数字逻辑电路获取精确时间戳，并实现同步算法、晶振补偿算法和状态转移控制算法，利用晶振分频比微调减小晶振频率漂移对同步精度和稳定性的影响。仿真结果表明，该设计具有较高的同步精度，精度值可达10 ns。

关键词: 精确时间协议, IP核, 同步, 状态转移控制

CLC Number: 

• TP331