Abstract: Aiming at the consideration of improving the utilizing efficiency of off-chip bandwidth and resolving “Memory Wall” problem, this paper designs a Data-Parallel Memory System(DPMS) for the tiled stream processor in current project. This memory system can reduce the time costs of off-chip memory access and meet the needs of off-chip bandwidth. Results of software simulation and emulation verification indicate that for different workloads, the design can fully capture the row-locality and bank-parallelism of memory access, by optimizing the configuration parameters and further boost the utilizing efficiency of DRAM bandwidth.

Key words: tiled stream processor, Data-Parallel Memory System(DPMS), off-chip bandwidth

摘要： 针对“存储墙”问题，从提高片外带宽使用率的角度出发，为分片式流处理器设计实现数据并行存储系统。该存储系统通过多级调度能有效减少片外访存的次数，降低片外带宽的需求。软件模拟和仿真验证的结果表明，在不同工作负载特征下，通过设计参数的优化选择，该设计能够充分挖掘存储访问的行局部性和体间并行性，从而提高带宽的使用效率。

关键词: 分片式流处理, 数据并行存储系, 片外带宽

CLC Number: 

• N945