[1] Acosta C, Cazorla F J, Ramirez A, et al. MFLUSH: Handling Long-latency Loads in SMT On-chip Multiprocessors[C]//Proc. of the 37th International Conference on Parallel Processing. Portland, Oregon, USA: [s. n.], 2008.
[2] Hasan J, Jalote A, Vijaykumar T N, et al. Heat Stroke: Power-density-based Denial of Service in SMT[C]//Proc. of HPCA’05. San Francisco, CA, USA: [s. n.], 2005: 166-177.
[3] Tullsen D, Eggers S J, Levy H M. Simultaneous Multithreading: Maximizing On-chip Parallelism[C]//Proc. of ISCA’95. Santa Margherita Ligure, Italy: [s. n.], 1995.
[4] Brooks D, Tiwari V, Martonosi M. Wattch: A Framework for Architectural-level Power Analysis and Optimizations[C]//Proc. of ISCA’00. New York, USA: [s. n.], 2000.
[5] Sharkey J J, Ponomarev D, Ghose K. M-SIM: A Flexible, Multithreaded Architectural Simulation Environment[R]. New York, USA: State University of New York at Binghamton, Tech. Rep.: CS-TR-05-DP01, 2005.
[6] 何立强, 刘志勇. 基于负载瞬时IPC性能的同时多线程处理器取指策略[J]. 计算机学报, 2007, 30(4): 629-637.
[7] Deepak B M I, Lakshmi N B, Madhu S S G. Functional Unit Usage Based Thread Selection in a Simultaneous Mutithreaded Processor[C]//Proc. of HIPC’06. [S. l.]: IEEE Press, 2006.
[8] Park S, Shrivastava A, Dutt N. Bypass Aware Instruction Scheduling for Register File Power Reduction[C]//Proc. of LCTES’06. Ottawa, Ontario, Canada: [s. n.], 2006. |