Design and Implementation of TOE Network Interface Card   Based on FPGA

doi:10.3969/j.issn.1000-3428.2011.03.085

Computer Engineering ›› 2011, Vol. 37 ›› Issue (3): 241-243,247. doi: 10.3969/j.issn.1000-3428.2011.03.085

• Networks and Communications • Previous Articles Next Articles

Design and Implementation of TOE Network Interface Card Based on FPGA

ZHAO Xi-quan, LIU Xing-kui, SHAO Zong-you, LIU Chao-hui, DOU Xiao-guang, ZHAO Xiao-fang

(Institute of Computing Technology, China Academy of Sciences, Beijing 100190, China)

Online:2011-02-05 Published:2011-01-28

基于FPGA的TOE网卡设计与实现

赵喜全，刘兴奎，邵宗有，刘朝辉，窦晓光，赵晓芳

(中国科学院计算技术研究所，北京 100190)

作者简介:赵喜全(1984－)，男，硕士，主研方向：计算机系统结构；刘兴奎，博士研究生；邵宗有，高级工程师；刘朝辉、窦晓光，硕士；赵晓芳，高级工程师
基金资助:
国家“863”计划基金资助重大项目“一体化安全管理和系统”(2007AA01Z467)

Abstract

Abstract: To alleviate the burden of CPU and improve system performance, a TCP Offload Engine(TOE) system based on Field Programmable Gate Array(FPGA) is designed and implemented. This TOE network adaptor adopts a hardware solution to implement some TCP protocol software dataflow processing, such as packet classification and TCP stream reassembly. Test results show that TOE network adaptor can greatly decline host’s CPU utilization.

Key words: TCP Offload Engine(TOE), hardware acceleration, TCP stream reassembly, Field Programmable Gate Array(FPGA)

摘要： 为进一步减轻CPU的负担，有效增加系统性能，描述一种基于FPGA的TCP减负引擎系统的设计与实现。该TOE网卡将部分TCP协议软件处理下移到FPGA中实现，以硬件的方法实现报文分类和TCP流还原等流量处理功能。实验数据表明，使用TOE网卡可以大幅降低主机的CPU占用率。

关键词: TCP减负引擎, 硬件加速, TCP流还原, 现场可编程门阵列

CLC Number:

TP303

DIAO Chi-Quan, LIU Xin-Kui, SHAO Zong-Wei, LIU Chao-Hui, DOU Xiao-Guang, DIAO Xiao-Fang. Design and Implementation of TOE Network Interface Card Based on FPGA[J]. Computer Engineering, 2011, 37(3): 241-243,247.

赵喜全, 刘兴奎, 邵宗有, 刘朝辉, 窦晓光, 赵晓芳. 基于FPGA的TOE网卡设计与实现[J]. 计算机工程, 2011, 37(3): 241-243,247.

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