Abstract: This paper proposes a hardware pipelining processor for single-threads with granularity of code block. It makes use of compile technique to parallel program and divides program into blocks. Some blocks are arranged to be executed at processor’s idle units to improve performance. The processor needs compiler support, but has less of modification to primary processor. Results show that spec2000 test program gets 40% performance improvement after using this processor.

Key words: hardware pipelining structure, circulation and acceleration, parallel execution, ISA expansion

摘要： 利用核内空闲资源加速单线程程序执行的方法，将可并行的代码安排在核内空闲单元上执行，实现代码块在核内的流水操作，从而设计一种具有循环加速能力的硬件流水处理器，可通过改变取值结构和寄存器分配逻辑获得编译器的支持。结果表明，应用该处理器后的spec2000测试程序执行性能提升了40%。

关键词: 硬件流水结构, 循环加速, 并行执行, ISA扩展

CLC Number: 

• TP393