Abstract: The memory management unit and the Cache of S3C2440A are introduced. An experimental method is designed to measure the influence of Cache on the instruction executive speed while the cache is disabled or enabled. Plenty of experiments are accomplished for instructions located in SDRAM or SRAM under three recommendatory CPU frequencies, data are analyzed and processed. Experimental results show that it has great influence to improve instruction mean executive speed when the cache is enabled.

Key words: Cache, Memory Management Unit(MMU), instruction, microprocessor

摘要： 介绍ARM微处理器S3C2440A的内存管理单元(MMU)和高速缓存，设计一种实验方法来测定在不同CPU时钟频率下禁用或启用高速缓存时，程序指令在SDRAM和SRAM中的平均执行速度，并对数据进行分析和处理。实验结果表明，启用高速缓存对提高指令的平均执行速度具有较大影响。

关键词: 高速缓存, 内存管理单元, 指令, 微处理器

CLC Number: 

• TP368.1