Abstract:
This paper presents a highly-parallel Turbo decoder architecture. It utilizes 32-parallel radix-4 component decoders and its throughput is increased by 43.2% at most with modified sliding window and memory partition scheme. The proposed decoder is implemented in SMIC 0.13 μm technology, which has 1.94 M equivalent gate counts and achieves 1.19 Gb/s running at 294 MHz with 5.5 iterations. It meets the peak data rate requirement of 4G mobile communication standard LTE-Advanced.
Key words:
Turbo code,
decode,
parallel architecture,
radix-4,
4G mobile communication
摘要: 提出一种高度并行的Turbo译码器。该译码器包含32个并行的基-4子译码器,采用改进的滑窗译码流程和存储单元划分方案,使吞吐率最高提升43.2%。在SMIC 0.13 μm工艺下,该译码器包含194万等效门,在294 MHz时钟频率和5.5次迭代下,吞吐率可达 1.19 Gb/s,满足4G移动通信标准LTE-Advanced的峰值吞吐率要求。
关键词:
Turbo码,
译码器,
并行结构,
基-4,
4G移动通信
CLC Number:
CHEN Xu-Bin, CAO Jia-Lin, CHEN Bin, CENG Xiao-Xiang. VLSI Design of High Performance Parallel Turbo Decoder[J]. Computer Engineering, 2012, 38(23): 255-258.
陈绪斌, 曹嘉麟, 陈赟, 曾晓洋. 高性能并行Turbo译码器的VLSI设计[J]. 计算机工程, 2012, 38(23): 255-258.