Study of Modulation Waveform Cycle Normalization PWM Based on FPGA

doi:10.3969/j.issn.1000-3428.2014.11.059

Computer Engineering

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Study of Modulation Waveform Cycle Normalization PWM Based on FPGA

JIANG Chao,HU Yueli

(School of Mechatronic Engineering and Automation,Shanghai University,Shanghai 200072, China)

Received:2013-09-18 Online:2014-11-15 Published:2014-11-13

基于FPGA 的调制波周期归一化PWM 研究

江　超,胡越黎

(上海大学机电工程与自动化学院,上海200072)

作者简介:江　超(1987 - ),男,硕士研究生,主研方向:汽车电子,PWM 控制自动化,现场可编程门阵列; 胡越黎,教授、博士、博士生导师。
基金资助:
国家自然科学基金资助项目“硅基有机发光微显示器的高性能顶发射界面及数字驱动研究”(61376028);上海市科委基金资助项目“高清硅基OLED 微显示器件设计制造技术”(13111104600)。

Abstract

Abstract: A novel Pulse Width Modulation(PWM) waveform generating method based on modulation waveform cycle normalization is proposed. Mapping between address storing data in digital system and pulse width of PWM waveform is the key essence. According to it,a system based on Field Programmable Gate Array(FPGA) is designed and implemented,and difficulties like analog digitization, modulation ratio M, carrier ratio N and details for modulation waveform cycle normalization digitization are solved. With setting modulation waveform Pn for PWM,a specific PWM waveform based on modulation waveform cycle normalization can be achieved successfully,which shows the effectiveness of the method.

Key words: modulation waveform cycle normalization, Pulse Width Modulation(PWM), modulation ratio, carrier wave ratio, Field Programmable Gate Array(FPGA)

摘要： 研究调制波周期归一化脉冲宽度调制(PWM),把数字系统中用于记录存储数据Ram 的地址Address 与PWM 脉冲宽度相互映射,给出一般性结论。基于这一模型结构,设计调制波周期归一化PWM 的现场可编程门阵列数字系统。针对设计该数字系统时出现的包括模拟量数字化、调制比M、载波比N 以及调制波周期归一化PWM各环节具体数字化实现等问题予以分析并解决。对周期脉冲值Pn 进行简单设置,便可快速实现调制波周期归一化PWM 模型结构的波形输出。

关键词: 调制波周期归一化, 脉冲宽度调制, 调制比, 载波比, 现场可编程门阵列

CLC Number:

TP391

JIANG Chao,HU Yueli. Study of Modulation Waveform Cycle Normalization PWM Based on FPGA[J]. Computer Engineering, doi: 10.3969/j.issn.1000-3428.2014.11.059.

江超,胡越黎. 基于FPGA 的调制波周期归一化PWM 研究[J]. 计算机工程, doi: 10.3969/j.issn.1000-3428.2014.11.059.

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References

参考文献 [ 1 ]　Schonung A, Stemmler H. Static Frequency Changers with Subharmonic Control in Conjunction with Reversible Variable Speed AC Drives[J]. Brown Boveri Rev． ,1964,51(8/ 9):555-577. [ 2 ]　Rashid M H. Power Electronics Handbook [ M ]. [S. l． ]:Academic Press,2001. [ 3 ]　Holmes D G,Lipo T A. Pulse Width Modulation for Power Converters [ M ]. [ S. l． ]: IEEE Press, 2003: 95-152. [ 4 ]　Bowes S R,Bird B M. Novel Approach to the Analysis and Synthesis of Modulation Processes in Power Converters [ J ]. IEEE Proceedings, 1975, 122 ( 5 ): 507-513. [ 5 ]　Bowes S R. New Sinusoidal Pulse-width Modulated Inverter [ J ]. IEEE Proceedings, 1975, 122 ( 11 ): 1279-1285. [ 6 ]　Bowes S R,Midoun A. New PWM Switching Strategy for Microprocessor-controller Inverter Drives [J]. IEEE Proceedings,1986,133(4):237-254. [ 7 ]　Bowes S R,Holliday D. Optimal Regular-sampled PWM Inverter Control Techniques [J]. IEEE Transactions on Industrial Electronics,2007,54(3):1547-1559. [ 8 ]　Khluabwannarat P,Thammarat C,Tadsuan S,et al. An Analysis of Iron Loss Supplied by Sinusoidal, Square Wave, Bipolar PWM Inverter and Unipolar PWM Inverter[C] / / Proc. of Power Engineering Conference. [S. l． ]:IEEE Press,2007:1185-1190. [ 9 ]　王立乔. 正弦波逆变器脉宽调制技术的调制模型分析 [J]. 电力系统自动化,2008,32(7):45-49,99. [10]　李　涛,张晓锋,乔鸣忠. SPWM 与SVPWM 的宏观对等性研究[J]. 中国电机工程学报,2010,30 (s1): 178-184. [11]　郭　涛,孙玉坤,任明炜,等. 链式多电平变换器特定谐波消除脉宽调制方法研究[J]. 电力自动化设备, 2006,26(12):52-54,101. [12]　马丰民,吴正国,侯新国. 基于统一PWM 调制器的随机空间矢量调制[J]．中国电机工程学报,2007,27 (7):98-102. [13]　刘晓东,徐　弢. 正弦脉宽调制技术开关时间点精度分析[J]. 电力自动化设备,2010,30(12):55-59. [14]　伍家驹,王文婷,李学勇,等. 单相SPWM 逆变桥输出电压的谐波分析[J]. 电力自动化设备,2008,28(4): 45-49,52. [15]　Hu Yueli,Zhou Chen. Integration and Verification Case of IP-core Based System on Chip Design[J]. Journal of Shanghai University ( English Edition),2010,14 (5): 349-353. [16]　王　奔,仇乐兵,徐万良,等. 基于FPGA 的空间矢量脉冲宽度调制发生器设计[J]. 电力自动化设备, 2012,32(2):56-61. 编辑　顾逸斐

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