Design and Implementation of Simulation Verification Platform for PCIE Protocol Stack

doi:10.3969/j.issn.1000-3428.2015.06.052

Computer Engineering

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Design and Implementation of Simulation Verification Platform for PCIE Protocol Stack

ZHANG Liang¹,WANG Tiancheng ²,WANG Jian ^2,3,LI Huawei ²,GUO Jian ¹

(1. Faculty of Materials,Optoelectronics and Physics,Xiangtan University,Xiangtan 411105,China; 2. State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences, Beijing 100190,China; 3. University of Chinese Academy of Sciences,Beijing 100049,China)

Received:2014-05-07 Online:2015-06-15 Published:2015-06-15

PCIE 协议栈模拟验证平台的设计和实现

张　良¹,王天成²,王　健^2,3,李华伟²,郭　建¹

(1. 湘潭大学材料与光电物理学院,湖南湘潭411105; 2. 中国科学院计算技术研究所计算机体系结构国家重点实验室,北京100190; 3. 中国科学院大学,北京100049)

作者简介:张　良(1989 - ),男,硕士研究生,主研方向:集成电路设计;王天成,工程师;王　健,博士研究生;李华伟,研究员;郭　建,教授。
基金资助:
国家自然科学基金资助项目(61233010)。

Abstract

Abstract:

Intel’s third generation of PCI Express bus technology can satisfy the requirements to the development of the computer system from the bus bandwidth on the structure,which leads to the vigorous development of IC design based on PCIE. The verification of the PCIE becomes an important part of function verification of the SoC. This paper designs and implements an automatic verification platform driven by combination both state graph and coverage, which mainly includes the mechanism of test generation,automatic check and coverage analysis. It uses the platform to verify the function of a protocol stack chips based on PCIE. Experimental results show that the verification platform has a good stimulus generation mechanism,which can conduct a comprehensive verification of the protocol stack chip design. In addition,the platform has the advantage of good reusability and expandability,which can verify the system of the multiple protocol stack interconnected.

Key words: functional verification, PCIE protocol stack, protocol stack verification, functional coverage rate, constrained random simulation, stimulus genertion

摘要：

Intel 提出的第三代总线技术PCI Express 在结构上可以满足计算机系统的发展对总线带宽的要求,基于 PCIE 的设计得以蓬勃发展,对PCIE 的验证也成为SoC 功能验证的重要组成部分。为此,设计并实现一种状态图和覆盖率组合驱动的自动化验证平台,主要包括激励生成、自动检测和覆盖率分析机制,并将其应用于一款基于 PCIE 接口的协议栈芯片的功能验证。实验结果表明,该验证平台具有较好的激励生成机制,能够对协议栈芯片进行全面验证,同时具有较好的复用性、可扩展性,可以对多个协议栈的互连进行验证。

关键词: 功能验证, PCIE 协议栈, 协议栈验证, 功能覆盖率, 约束随机模拟, 激励生成

CLC Number:

TP331

ZHANG Liang,WANG Tiancheng,WANG Jian,LI Huawei,GUO Jian. Design and Implementation of Simulation Verification Platform for PCIE Protocol Stack[J]. Computer Engineering, doi: 10.3969/j.issn.1000-3428.2015.06.052.

张良,王天成,王健,李华伟,郭建. PCIE 协议栈模拟验证平台的设计和实现[J]. 计算机工程, doi: 10.3969/j.issn.1000-3428.2015.06.052.

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References

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