Byte Addressing Mode Expansion and 64bit Data Operation Simulation Implementation for BWDSP104X

doi:10.3969/j.issn.1000-3428.2016.08.003

Abstract

Abstract: Currently,the programming model under BWDSP104X compiler is based on the word unit addressing modes,lacking of support for non 32-bit wide data and incompatible with byte unit addressing modes.With the modification of related frontend data type,the intermediate code based on byte addressing mode is generated.A series of 32-bit machine instructions is outputted by backend to fulfill byte address transformation or data manipulation,and the expansion of byte addressing mode is implemented.Register pairs are used to simulate 64-bit data access and operation,improving the accuracy of floatingpoint data operation.Experimental results show that the compiler is compatible with the byte addressing mode as well as the 64-bit floatingpoint data type.It can well meet the requirement of highspeed realtime signal processing.

Key words: compiler, word addressing, byte addressing, byte alignment, 64-bit data operation, register pair

摘要： 目前BWDSP104X编译器的编程模型支持以字为单位的寻址方式,不支持非32位宽数据并且不兼容以字节为单位的寻址模式。通过对BWDSP104X前端相关数据类型进行修改,产生基于字节寻址模式的中间代码,而后端由此输出一系列32位机器指令来完成对应的字节地址转换或数据操作,从而实现字节寻址模式的扩展。利用寄存器对模拟实现64位数据的存取与运算,提高浮点数据运算的精度。实验结果表明,该编译器兼容字节寻址模式以及64位浮点数据类型,能较好地满足高速实时信号处理的需求。

关键词: 编译器, 字寻址, 字节寻址, 字节对齐, 64位数据运算, 寄存器对

CLC Number:

TP391

ZHAO Gaoyi,ZHENG Qilong. Byte Addressing Mode Expansion and 64bit Data Operation Simulation Implementation for BWDSP104X[J]. Computer Engineering, doi: 10.3969/j.issn.1000-3428.2016.08.003.

赵高义,郑启龙. BWDSP104X字节寻址模式扩展及64位数据运算模拟实现[J]. 计算机工程, doi: 10.3969/j.issn.1000-3428.2016.08.003.

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References

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