Abstract: Network on a Chip(NoC) typically uses the input output buffer or cross switch buffer to store the microchip.Although this improves the performance of router,it consumes many resources and significantly increases the power consumption.For this problem,bufferless router is proposed.Because of the existence of the inefficient deflection of microchips in bufferless router,it is not suitable for medium and high load networks.Hence,this paper proposes a new mini-buffered router with low deflection rate based on directional vector routing strategy.It uses a bypass register and a loopback register,and uses the maximum bipartite graph matching scheduling algorithm to optimize the microchip routing.Simulation and synthesis on Xilinx’s Vivado show that the performance of this router is quite similar to that of RIDER router,but the register usage is reduced by 55%,and the performance is better than that of CHIPPER,MinBD and RIDER in high load network.

Key words: Network on a Chip(NoC), deflection routing, directional routing, bipartite graph matching, mini-buffered router

摘要： 片上网络通常使用输入输出缓存或交叉开关缓存存储微片以提高路由器性能,导致大量消耗片上资源并显著增加功耗。无缓存路由器被提出用于解决该问题,但存在低效率的偏转,不适用于中、高负载的网络。为此,设计一种基于方向向量路由策略的低偏转率微缓存路由器。采用一个旁路寄存器和一个回环寄存器的设计,通过二分图最大匹配调度算法优化微片路由。在Xilinx Vivado上的仿真结果表明,该路由器的性能与RIDER路由器相当,但寄存器使用减少55%,并且在高负载网络中性能优于CHIPPER,MinBD和RIDER路由器。

关键词: 片上网络, 偏转路由, 方向路由, 二分图匹配, 微缓存路由器

CLC Number: 

• TP393