参考文献
[1] 阎 毅. 软件无线电与认知无线电概论[M]. 北京: 电子工业出版社, 2012.
[2] Blake G, Deslinski R G, Mudge T. A Survey of Multicore Processors: A Review of Their Common Attributes[J]. IEEE Signal Processing Magazine, 2009, 26(6): 26-37.
[3] Wu A S, Yu Han, Jin Shiyuan, et al. An Incremental Genetic Algorithm Approach to Multiprocessor Scheduling[J]. IEEE Transactions on Parallel and Distributed Systems, 2004, 15(9): 824-834.
[4] Topcuoglu H, Hariri S, Wu Minyou. Performance-effective and Low-complexity Task Scheduling for Heterogeneous Computing[J]. IEEE Transactions on Parallel and Distributed Systems, 2002, 13(3): 260-274.
(下转第97页)
(上接第87页)
[5] Radulescu A,. Fast and Effective Task Scheduling in Hetero- geneous Systems[C]//Proceedings of the 9th Heterogeneous Computing Workshop. Cancun, Mexico: [s. n.], 2000.
[6] 施汝杰, 高佩君, 田佳音, 等. ZigBee网络节点基带处理器的设计与实现[J]. 计算机工程, 2008, 34(17): 219-221.
[7] Lee E, Messerschmitt D. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing[J]. IEEE Transactions on Computers, 1987, 32(1): 24-35.
[8] Tran A, Truong D, Baas B. A Reconfigurable Source- synchronous On-chip Network for GALS Many-core Platforms[J]. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2010, 29(6): 897-910.
[9] Bell S, Edwards B, Amann J, et al. TILE64-processor: A 64-core SoC with Mesh Interconnect[C]//Proceedings of IEEE International Solid-state Circuits Conference. San Francisco, USA: [s. n.], 2008.
[10] Bender A. Design of an Optimal Loosely Coupled Hetero- geneous Multiprocessor System[C]//Proceedings of European Design and Test Conference. Paris, France: [s. n.], 1996.
[11] Yi Ying, Han Wei, Zhao Xin. An ILP Formulation for Task Mapping and Scheduling on Multi-core Architectures[C]// Proceedings of Design, Automation & Test in Europe Conference & Exhibition. Nice, France: [s. n.], 2009.
[12] Limberg T, Winter M, Bimberg M, et al. A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio[C]//Proceedings of the Design Automation Conference. San Francisco, USA: [s. n.], 2009.
[13] Ostler C, Chatha K. An ILP Formulation for System-level Application Mapping on Network Processor Architec- tures[C]//Proceedings of Design, Automation & Test in Europe Conference & Exhibition. Nice, France: [s. n.], 2007.
编辑 陆燕菲 |