计算机工程 ›› 2018, Vol. 44 ›› Issue (10): 85-94,100.doi: 10.19678/j.issn.1000-3428.0048482

• 体系结构与软件技术 • 上一篇    下一篇

支持指令预取的多核缓存WCET分析方法

安立奎a,韩丽艳b   

  1. 渤海大学 a.数理学院; b.信息科学与技术学院,辽宁 锦州 121013
  • 收稿日期:2017-08-31 出版日期:2018-10-15 发布日期:2018-10-15
  • 作者简介:安立奎(1978—),男,讲师、硕士,主研方向为计算机体系结构、实时计算;韩丽艳,讲师、硕士。
  • 基金项目:
    辽宁省科学技术计划项目“面向复杂海量数据的信息获取方法研究”(LN2014160)。

Cache WCET Analysis Method with Instruction Prefetching on Multi-cores

AN Likuia,HAN Liyanb   

  1. a.School of Mathematics and Physics; b.School of Information Science and Technology, Bohai University,Jinzhou,Liaoning 121013,China
  • Received:2017-08-31 Online:2018-10-15 Published:2018-10-15

摘要: 为确保硬实时任务满足时间截止期,需要分析硬实时任务的支持指令预取缓存,而现有方法多数仅限于单级指令缓存,不能用于嵌入式多核下支持指令预取的多级缓存分析。为此,在基于组缓存划分的多核模型下,通过对抽象解释的缓存分析模型进行指令预取语义扩展,提出一种支持指令预取的多核缓存分析方法。实验结果表明,该方法安全性较高,能够提高多核下硬实时任务的预取缓存性能。

关键词: 嵌入式多核, 硬实时任务, 最差情况执行时间, 指令预取, 缓存划分

Abstract: In order to ensure Hard Real-time Task(HRT) to meet deadlines,their Worst Case Execution Time(WCET) with instruction prefetching need to be analyzed.Although the cache analysis methods with instruction prefetching in single-core have already existed,the researches are limited on the single-level instruction cache and they cannot be applied on the multi-level cache WCET analysis on multi-cores.Through extending instruction prefetching semantic for multi-level cache analysis model based on abstract interpretation,this paper puts forward a cache analysis method with instruction prefetching on the multi-cores model based on set cache partitioning.Experimental results verify the method has high safety and can improve the prefetching cache performance of multi-core HRT.

Key words: embedded multi-cores, Hard Real-time Task(HRT), Worst Case Execution Time(WCET), instruction prefetching, cache partitioning

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