计算机工程 ›› 2020, Vol. 46 ›› Issue (5): 167-173,180.doi: 10.19678/j.issn.1000-3428.0054776

• 网络空间安全 • 上一篇    下一篇

一种面向密码SoC的高性能全双工DMA设计

吕广秋, 李伟, 陈韬, 南龙梅   

  1. 信息工程大学 信息安全重点实验室, 郑州 450001
  • 收稿日期:2019-04-29 修回日期:2019-07-08 发布日期:2019-07-17
  • 作者简介:吕广秋(1994-),男,硕士研究生,主研方向为网络信息安全、集成电路设计;李伟(通信作者),副教授、博士生导师;陈韬、南龙梅,副教授。
  • 基金项目:
    国家自然科学基金(61404175)。

A High Performance Full Duplex DMA Design for Cryptographic SoC

Lü Guangqiu, LI Wei, CHEN Tao, NAN Longmei   

  1. Key Laboratory of Information Security, Information Engineering University, Zhengzhou 450001, China
  • Received:2019-04-29 Revised:2019-07-08 Published:2019-07-17

摘要: 在密码SoC等数据密集型应用中,数据传输速度成为制约密码处理性能提升的瓶颈。结合密码SoC的数据流处理特点,提出一种面向密码SoC的高性能DMA优化设计方法。对特定模块的DMA传输开辟专用通道,利用并行读写数据提高特定模块DMA传输的总线带宽利用率。添加特殊工作模式用于自主控制重复任务传输以提升传输的带宽利用率。在此基础上,采用多通道优先级动态调整技术实现多任务下效率较高的自适应传输。仿真结果表明,该DMA在55 nm工艺下的最高频率达910 MHz,总线利用率和协处理器利用率的平均值分别高达91%和54%,相对通用DMA,其对密码SoC的ZUC、SNOW、SM3、SM4和AES算法的性能分别提升216%、222%、123%、69%和221%。

关键词: 带宽利用率, 读写并行, 循环传输, 动态优先级, 自适应传输

Abstract: In data-intensive applications such as cryptographic SoC,data transmission speed has gradually become a bottleneck restricting cipher processing performance.To address the problem,this paper proposes an optimized high performance DMA design method for cryptographic SoC based on the characteristics of stream processing in cryptographic SoC.First,a dedicated channel for DMA transfer of a specific module is opened,and data is read/written in parallel to improve the utilization rate of bus bandwidth in DMA transmission of a specific module.Second,a special work mode is added for autonomous control of repeated task transmission,so as to improve the utilization rate of transmission bandwidth.On this basis,dynamic adjustment technology based on multi-channel priority optimization is used to achieve more efficient adaptive transmission under multiple tasks.Simulation results show that the highest frequency of the proposed DMA in the 55 nm process is 910 MHz.The average utilization rate of bus and the coprocessor is 91% and 54% respectively.Compared with the general design of DMA,the proposed design increases the performance of ZUC,SNOW,SM3,SM4 and AES algorithms to cryptographic SoC by 216%,222%,123%,69% and 221% respectively.

Key words: bandwidth utilization rate, read/write in parallel, cyclic transmission, dynamic priority, adaptive transmission

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