超标量处理器乱序提交机制的研究与设计

doi:10.19678/j.issn.1000-3428.0057410

计算机工程 ›› 2021, Vol. 47 ›› Issue (4): 180-186. doi: 10.19678/j.issn.1000-3428.0057410

超标量处理器乱序提交机制的研究与设计

李昭¹, 刘有耀¹, 焦继业², 潘树朋¹

1. 西安邮电大学电子工程学院, 西安 710100;
2. 西安邮电大学计算机学院, 西安 710100

收稿日期:2020-02-17 修回日期:2020-04-02 发布日期:2020-04-10
作者简介:李昭(1993-),男,硕士研究生,主研方向为专用集成电路设计;刘有耀,教授、博士;焦继业,高级工程师、博士;潘树朋,硕士研究生。
基金资助:
国家自然科学基金（61874087，61834005，61634004）。

Research and Design of Out-of-Order Submission Mechanism for Superscalar Processor

LI Zhao¹, LIU Youyao¹, JIAO Jiye², PAN Shupeng¹

1. School of Electronic Engineering, Xi'an University of Posts & Telecommunications, Xi'an 710100, China;
2. School of Computer Science & Technology, Xi'an University of Posts & Telecommunications, Xi'an 710100, China

Received:2020-02-17 Revised:2020-04-02 Published:2020-04-10

摘要/Abstract

摘要： 针对超标量处理器中长周期执行指令延迟退休及持续译码导致的重排序缓存（ROB）阻塞问题，提出一种指令乱序提交机制。通过设计容量可配置的多缓存指令提交结构，实现存储器操作指令和ALU类型指令的分类退休，根据超标量处理器架构及性能需求对目标缓存和存储缓存容量进行参数化配置降低流水线阻塞风险，同时利用指令目的寄存器编码提交模式加快指令提交速率。实验结果表明，该机制提高了单次指令提交数量，基于该机制的超标量处理器相比传统基于ROB顺序提交机制的超标量处理器在减少硬件开销的情况下平均IPC指数提升46%，相比基于值预测、乱序退休和组提交的超标量处理器平均IPC指数增益为19%，综合性能更优。

关键词: 超标量处理器, 重排序缓存, 指令分类退休, 乱序提交, 目的寄存器编码

Abstract: To address blocking of Reorder Buffer(ROB) caused by delayed retirement of long-term execution instructions and continuous decoding in the superscalar processors,this paper proposes a mechanism for out-of-order submission of instructions.This mechanism designs a multi-buffer instruction submission structure with configurable capacity to implement classified retirement of memory operation instructions and ALU instructions.Based on the structure and performance requirements of superscalar processors,parameterized configuration is performed on the Target Buffer(TB) capacity and Memory Buffer(MB) capacity to reduce the risk of streamline blocking.In addition,the encoding submission mode of instruction destination register is used to accelerate instruction submission.Experimental results show that the proposed mechanism increases the number of single instruction submissions.The superscalar processor based on the proposed mechanism improves the average IPC index by 46% compared with the traditional ROB-based superscalar processor while the hardware overhead is reduced,and by 19% compared with the superscalar processors based on ratio prediction,out-of-order retirement,and group submission schemes.It has better comprehensive performance.

Key words: superscalar processor, Reorder Buffer(ROB), instruction classification retirement, out-of-order submission, destination register encoding

中图分类号:

TP338

李昭, 刘有耀, 焦继业, 潘树朋. 超标量处理器乱序提交机制的研究与设计[J]. 计算机工程, 2021, 47(4): 180-186.

LI Zhao, LIU Youyao, JIAO Jiye, PAN Shupeng. Research and Design of Out-of-Order Submission Mechanism for Superscalar Processor[J]. Computer Engineering, 2021, 47(4): 180-186.

http://www.ecice06.com/CN/Y2021/V47/I4/180

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