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计算机工程 ›› 2007, Vol. 33 ›› Issue (22): 23-25. doi: 10.3969/j.issn.1000-3428.2007.22.009

• 博士论文 • 上一篇    下一篇

一种多功能阵列乘法器的设计方法

胡正伟1,2,仲顺安1   

  1. (1. 北京理工大学电子工程系,北京 100081;2. 华北电力大学电子与通信工程学院,保定 071003)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-11-20 发布日期:2007-11-20

Design Method for Multi-function Array Multiplier

HU Zheng-wei1,2, ZHONG Shun-an1   

  1. (1. Departerment of Electronic Engineering, Beijing Institute of Technology, Beijing 100081; 2. School of Electronic and Communication Engineering, North China Electric Power University, Baoding 071003)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-11-20 Published:2007-11-20

摘要: 为了实现不同数制的乘法共享硬件资源,提出了一种可以实现基于IEEE754标准的64位双精度浮点与32位单精度浮点、32位整数和16位定点的多功能阵列乘法器的设计方法。采用超前进位加法和流水线技术实现乘法器性能的提高。设计了与TMS320C6701乘法指令兼容的乘法单元,仿真结果验证了设计方案的正确性。

关键词: 阵列乘法器, 浮点, 超前进位, 流水线

Abstract: A new design method for multi-function array multiplier is proposed, which can work using different data styles. These styles are 64bits double precision floating point data, 32bits single precision floating point data, 32bits integer data and 16bits fixed point data. By using pipeline structure and carry look ahead addition method, the performance of this multi-function array multiplier can be enhanced distinctly. A multiplication unit whose instructions are compatible with TMS320C6701 is realized based on this method. The correctness and performance are confirmed by simulation results.

Key words: array multiplier, floating point, carry look ahead, pipeline

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