嵌入式RISC-V乱序执行处理器的研究与设计

doi:10.19678/j.issn.1000-3428.0057141

计算机工程 ›› 2021, Vol. 47 ›› Issue (2): 261-267,284. doi: 10.19678/j.issn.1000-3428.0057141

嵌入式RISC-V乱序执行处理器的研究与设计

李雨倩¹, 焦继业², 刘有耀¹, 郝振和²

1. 西安邮电大学电子工程学院, 西安 710121;
2. 西安邮电大学计算机学院, 西安 710121

收稿日期:2020-01-06 修回日期:2020-02-17 出版日期:2021-02-15 发布日期:2020-02-24
作者简介:李雨倩(1994-),女,硕士研究生,主研方向为嵌入式系统;焦继业,高级工程师;刘有耀,副教授;郝振和,硕士研究生。
基金资助:
国家自然科学基金（61874087）。

Research and Design of Embedded RISC-V Out-of-Order Execution Processor

LI Yuqian¹, JIAO Jiye², LIU Youyao¹, HAO Zhenhe²

1. School of Electronic Engineering, Xi'an University of Posts & Telecommunications, Xi'an 710121, China;
2. School of Computer Science and Technology, Xi'an University of Posts & Telecommunications, Xi'an 710121, China

Received:2020-01-06 Revised:2020-02-17 Online:2021-02-15 Published:2020-02-24

摘要/Abstract

摘要： 为满足嵌入式设备小面积高性能的需求，设计一种基于开源RISC-V指令集的32位可综合乱序处理器。处理器包括分支预测、相关性处理等关键技术，支持RISC-V基本整数运算、乘除法以及压缩指令集。采用具有顺序单发射、乱序执行、乱序写回等特性的三级流水线结构，运用哈佛体系结构及AHB总线协议，可满足并行访问指令与数据的需求。在Artix-7（XC7A35T-L1CSG324I）FPGA开发板上以50 MHz时钟频率完成功能验证，测试功耗为7.9 mW。实验结果表明，在SMIC 110 nm的ASIC技术节点上进行综合分析，并在同等条件下与ARM Cortex-M3等处理器进行对比，该系统面积减少64%，功耗降低0.57 mW，可用于小面积低功耗的嵌入式领域。

关键词: RISC-V指令集, 嵌入式应用, 乱序处理器, 微体系结构, 三级流水线

Abstract: In order to meet the high performance and small area requirements of embedded devices,this paper designs and implements a 32-bit integrated out-of-order processor based on open source RISC-V instruction set.The processor includes the design of key technologies such as branch prediction and correlation processing,supporting basic integer operations,multiplication,division and compressed instruction set of RISC-V.It adopts a 3-stage assembly line structure that is characterized by sequential single transmission,out-of-order execution,out-of-order write-back,etc.By taking the AHB bus protocol for on-chip bus and using Harvard architecture,the demands of parallel access to instructions and data can be met.The functional verification is completed on the ARTIX-7 (XC7A35T-L1CSG324i)FPGA development board with a clock frequency of 50 MHz,and the test power consumption is 7.9 mW.The experimental results is comprehensively analyzed on the SMIC 110 nm ASIC technology node,and compared with ARM Cortex-M3 processors under the same conditions.Results show that the system area is reduced by 64% and power consumption reduced by 0.57 mW,which demonstrates that it can be used in embedded devices that require small area and low power consumption.

Key words: RISC-V instruction set, embedded application, out-of-order processor, microarchitecture, three-stage assembly line

中图分类号:

TP332

李雨倩, 焦继业, 刘有耀, 郝振和. 嵌入式RISC-V乱序执行处理器的研究与设计[J]. 计算机工程, 2021, 47(2): 261-267,284.

LI Yuqian, JIAO Jiye, LIU Youyao, HAO Zhenhe. Research and Design of Embedded RISC-V Out-of-Order Execution Processor[J]. Computer Engineering, 2021, 47(2): 261-267,284.

http://www.ecice06.com/CN/Y2021/V47/I2/261

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