计算机工程 ›› 2008, Vol. 34 ›› Issue (7): 245-247.doi: 10.3969/j.issn.1000-3428.2008.07.087

• 工程应用技术与实现 • 上一篇    下一篇

多FPGA设计的时钟同步

宋 威1,2,方穗明1,姚 丹2,张立超2,钱 程2   

  1. (1. 北京工业大学电子信息与控制工程学院,北京 100022;2. 北京工业大学北京市嵌入式系统重点实验室,北京 100022)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2008-04-05 发布日期:2008-04-05

Clock Synchronization in Multi-FPGA Designs

SONG Wei1,2, FANG Sui-ming1, YAO Dan2, ZHANG Li-chao2, QIAN Cheng2   

  1. (1. College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing 100022; 2. Beijing Embedded System Key Lab, Beijing University of Technology, Beijing 100022)
  • Received:1900-01-01 Revised:1900-01-01 Online:2008-04-05 Published:2008-04-05

摘要: 在多FPGA设计中,时钟信号的传输延时造成了FPGA间的大时钟偏差,进而制约系统性能。为减少时钟偏差,该文提出一种多数字延迟锁相环(DLL)电路。该电路将时钟的传输电路放入DLL的反馈环路。利用DLL的延迟锁定特性,对FPGA间的时钟传输延时进行补偿,减少FPGA间的时钟偏差,解决多FPGA的时钟同步问题。

关键词: 现场可编程逻辑门阵列, 时钟偏差, 延迟锁相环

Abstract: In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance. To decrease this skew, a circuit based on Delayed Locked Loop(DLL) circuits is proposed. This circuit links the clock transfer path into the feedback loop of DLLs. Thanks to the delayed locked feature, the delay of clock transfer is compensated. Therefore, this circuit reduces the skew between FPGAs and solves the synchronization in multi-FPGA designs.

Key words: FPGA, clock skew, Delayecl Locked Loop(DLL)

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