计算机工程 ›› 2009, Vol. 35 ›› Issue (7): 212-214.doi: 10.3969/j.issn.1000-3428.2009.07.074

• 工程应用技术与实现 • 上一篇    下一篇

高速网络安全协处理器中PCI-X接口设计

朱 莹,白国强,陈弘毅

  

  1. (清华大学微电子学研究所信息科学与技术国家实验室,北京 100084)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-04-05 发布日期:2009-04-05

Design of PCI-X Interface for High Speed Network Security Co-processor

ZHU Ying, BAI Guo-qiang, CHEN Hong-yi

  

  1. (National Lab of Information Science & Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-04-05 Published:2009-04-05

摘要: 介绍高速网络安全协处理器中PCI-X接口模块的设计方法,利用IPSec和SSL/TLS 2种协议优化系统,并配置各种算法引擎。协处理器采用具有更高性能的PCI-X总线接口及SoC芯片,能够同时满足PCI-X总线协议和协处理器内部的特殊传输要求。实验结果表明,该设计方法是可行的。

关键词: PCI-X总线接口, 密码安全, 协处理器

Abstract: The method to design PCI-X interface for high speed network security co-processor is introduced, which uses two protocols such as IPSec and SSL/TLS protocols to optimize the system, and deploys different kinds of algorithm engines. The co-processor uses PCI-X bus interface and SoC chip with higher performance, which meets the requirement of both PCI-X bus protocol and the internal data transfers of co-processor. Experimental results show this method is feasible.

Key words: PCI-X bus interface, cipher security, co-processor

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