计算机工程 ›› 2009, Vol. 35 ›› Issue (8): 195-197.doi: 10.3969/j.issn.1000-3428.2009.08.066

• 安全技术 • 上一篇    下一篇

异步128位AES算法的硬件设计

崔亚磊1,唐为民2,戴紫彬1   

  1. (1. 解放军信息工程大学电子技术学院,郑州 450004;2. 北京交通大学计算机与信息技术学院,北京 100044)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-04-20 发布日期:2009-04-20

Hardware Design of Asynchronous 128-bit AES Algorithm

CUI Ya-lei1, TANG Wei-min2, DAI Zi-bin1   

  1. (1. Institute of Electronic Technology, PLA Information Engineering University, Zhengzhou 450004; 2. Institute of Computer and Information Technology, Beijing Jiaotong University, Beijing 100044)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-04-20 Published:2009-04-20

摘要: 基于四相握手协议设计异步流水线,实现单轮运算内流水操作,设计轮运算启动模块和异步控制信号生成模块,满足算法多轮运算的需要。在子密钥生成模块、字节替代模块和列混合模块使用复用技术,降低了对硬件的需求。在COMS 0.18 μm工艺下进行综合、布局布线和仿真,与采用同样数据路径设计方法的同步电路相比,吞吐率提高了12.5%。

关键词: AES算法, 异步, 四相握手协议, 异步流水线

Abstract: This paper designs an asynchronous pipeline based on the four-phare handshake protocol, realizes the pipeline in the round to satisfy the several rounds operations, and designs the round startup module and asynchronous control signal creating module. In the key expansion, subbytes, mixcolumns module, it uses the multiplexing technology to reduce the need of hardware. It has been fabricated with 0.18 μm CMOS process. Both the asynchronous design and its synchronous counterpart with the same data path are tested. The performance of the asynchronous design outdoes the synchronous circuit, and its throughput is increased by 12.5%.

Key words: AES algorithm, asynchronous, four-phare handshake protocol, asynchronous pipeline

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