摘要： 提出一种以硬件实现的各种条件为约束设计准循环的低密度奇偶校验码的校验矩阵方法，以简化硬件结构，采用行列交换及寻找最大平均环提升译码性能的方法。设计码长为1 200的校验矩阵，对该矩阵的译码电路进行RTL实现，采用SMIC0.13 μm标准CMOS工艺综合实现660 Mb/s吞吐率，面积为3.1 mm2，以该方法设计的矩阵可用于实现低复杂度的LDPC译码电路。

关键词: 低密度奇偶校验码, 校验矩阵, 层调度

Abstract: This paper presents a new method to design the parity matrix of QC Low Density Parity Check Code(QC-LDPC) with the constraints of hardware implementation. The exchanges in rows and columns are adopted to improve the performance. Matrixes with length of 1 200 designed by this method are used to be implemented with RTL code and synthesized with SMIC 0.13 μm standard CMOS technology. It can achieve throughput of 660 Mb/s and area of 3.1 mm2. It is proved that matrixes designed by this method can realize low complexity LDPC decoder circuit.

Key words: Low Density Parity Check Code(LDPC), parity matrix, layered schedule

中图分类号: 

• TP311