基于GPU的LDPC增强准最大似然译码器并行实现

doi:10.19678/j.issn.1000-3428.0056226

计算机工程 ›› 2020, Vol. 46 ›› Issue (5): 207-215. doi: 10.19678/j.issn.1000-3428.0056226

基于GPU的LDPC增强准最大似然译码器并行实现

孔飞跃¹, 蒋学芹¹, 万雪芬^2a,2b, 陈思井³, 崔剑⁴, 杨义¹

1. 东华大学信息科学与技术学院, 上海 201620;
2. 华北科技学院 a. 河北省物联网监控工程技术研究中心;b. 计算机学院, 河北廊坊 065201;
3. 武汉船舶通信研究所, 武汉 430205;
4. 北京航空航天大学网络空间安全学院, 北京 100083

收稿日期:2019-10-09 修回日期:2019-11-26 发布日期:2019-12-03
作者简介:孔飞跃(1993-),男,硕士研究生,主研方向为纠错码、GPU并行计算;蒋学芹,教授、博士生导师;万雪芬,讲师;陈思井,高级工程师;崔剑,讲师;杨义,副教授。
基金资助:
国家重点研发计划（2018YFC0808306）；河北省重点研发计划（19270318D）；河北省物联网监控工程技术研究中心项目（3142016020）；廊坊市科学技术研究与发展计划（2019011010）。

Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder

KONG Feiyue¹, JIANG Xueqin¹, WAN Xuefen^2a,2b, CHEN Sijing³, CUI Jian⁴, YANG Yi¹

1. College of Information Science and Technology, Donghua University, Shanghai 201620, China;
2a. Hebei IoT Monitoring Engineering Technology Research Center;2b. College of Computer, North China Institute of Science and Technology, Langfang, Hebei 065201, China;
3. Wuhan Maritime Communication Research Institute, Wuhan 430205, China;
4. School of Cyber Science and Technology, Beihang University, Beijing 100083, China

Received:2019-10-09 Revised:2019-11-26 Published:2019-12-03

摘要/Abstract

摘要： 增强准最大似然（EQML）译码器对于码长较短的低密度奇偶校验（LDPC）码的译码性能优于传统置信传播（BP）译码器，可较好满足5G移动通信的高可靠性要求，但由于其计算结构复杂导致译码速度大幅降低。为提高EQML译码器的译码速度，提出一种基于GPU的EQML译码器并行化加速方案，压缩并存储不规则LDPC码的奇偶校验矩阵，通过对传统BP译码算法进行重新排序以最大化利用Kernel中的线程，并对再处理过程中的每个阶段进行多码字并行译码，实现内存访问优化及流并行译码。实验结果表明，基于GPU的EQML译码器在保持纠错性能的同时，相比基于CPU的EQML译码器的译码速度约提升了2个数量级。

关键词: 低密度奇偶校验码, GPU并行译码, 增强准最大似然译码器, 置信传播译码器, 现场可编程门阵列

Abstract: The Enhanced Quasi-Maximum Likelihood(EQML) decoder has better decoding performance for short Low Density Parity Check(LDPC) codes than traditional Belief Propagation(BP) decoder,and can meet the high reliability requirements of 5G mobile communication.However,its decoding speed is greatly reduced due to its complex computational structure.To address the problem,this paper proposes a parallel acceleration scheme based on Graphics Processing Unit(GPU) for EQML decoder.The scheme compresses and stores the parity check matrix of irregular LDPC codes,and resorts the traditional BP decoding algorithms to maximize the utilization of threads in Kernel.Then parallel decoding is implemented for multi-code words in each stage of reprocessing,so as to realize memory access optimization and parallel decoding of streams.Experimental results show that the GPU-based EQML decoder improves the speed by two orders of magnitude compared with the CPU-based decoder,while keeping the error correction performance.

Key words: Low Density Parity Check(LDPC) code, GPU parallel decoding, Enhanced Quasi-Maximum Likelihood(EQML) decoder, Belief Propagation(BP) decoder, Field Programmable Gate Array(FPGA)

中图分类号:

TP391

孔飞跃, 蒋学芹, 万雪芬, 陈思井, 崔剑, 杨义. 基于GPU的LDPC增强准最大似然译码器并行实现[J]. 计算机工程, 2020, 46(5): 207-215.

KONG Feiyue, JIANG Xueqin, WAN Xuefen, CHEN Sijing, CUI Jian, YANG Yi. Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder[J]. Computer Engineering, 2020, 46(5): 207-215.

http://www.ecice06.com/CN/Y2020/V46/I5/207

图/表 16

20200513204245

20200513204249

20200513204256

20200513204302

20200513204306

20200513204311

20200513204315

20200513204320

20200513204325

20200513204330

20200513204334

20200513204338

20200513204342

20200513204346

20200513204352

20200513204359

参考文献

[1] AWAIS M,SINGH A,BOUTILLON E,et al.A novel architecture for scalable,high throughput,multi-standard LDPC decoder,in digital system design[C]//Proceedings of the 14th EUROMICRO Conference on Digital System Design.Washington D.C.,USA:IEEE Press,2011:340-347.
[2] VERMA S,SHARMA S.FPGA implementation of low complexity LDPC iterative decoder[J].International Journal of Electronics Letters,2015,103(7):1112-1126.
[3] BONCALO O,AMARICAI A,MIHANCEA P,et al.Memory trade-offs in layered self-corrected min-sum LDPC decoders[J].Analog Integrated Circuits and Signal Processing,2016,87(2):169-180.
[4] YAN Jiankang,CHEN Gengsheng.Improved H-Storm platform based on co-scheduling of CPU/GPU heterogeneous resource[J].Computer Engineering,2018,44(4):1-11.(in Chinese)严健康,陈更生.基于CPU/GPU异构资源协同调度的改进H-Storm平台[J].计算机工程,2018,44(4):1-11.
[5] CHEN Yong,WU Xiaomin,YANG Jian,et al.Design and implementation of H.264 parallel decoder based on CUDA[J].Computer Engineering,2016,42(5):249-252,257.(in Chinese)陈勇,吴晓民,杨坚,等.基于CUDA的H.264并行解码器设计与实现[J].计算机工程,2016,42(5):249-252,257.
[6] WANG G H,WU M,YIN B,et al.High throughput low latency LDPC decoding on GPU for SDR systems[C]//Proceedings of IEEE Global Conference on Signal and Information Processing.Washington D.C.,USA:IEEE Press,2013:1258-1261.
[7] YUAN Jinyang,SHA Jin.4.7-Gb/s LDPC decoder on GPU[J].IEEE Communications Letters,2018,22(3):478-481.
[8] ZHAO Y,LAU F.Implementation of decoders for LDPC block codes and LDPC convolutional codes based on GPUs[J].IEEE Transactions on Parallel and Distributed Systems,2014,25(3):663-672.
[9] HOU Yi,LIU Rongke,PENG Hao,et al.High throughput pipeline decoder for LDPC convolutional codes on GPU[J].IEEE Communications Letters,2015,19(12):2066-2069.
[10] LIN Yong,NIU Wensheng.High throughput LDPC decoder on GPU[J].IEEE Communications Letters,2014,18(2):344-347.
[11] KESKIN S,KOCAK T.GPU-based gigabit LDPC decoder[J].IEEE Communications Letters,2017,21(8):1703-1706.
[12] GAL B L,JEGO C,CRENNE J.A high throughput efficient approach for decoding LDPC codes onto GPU devices[J].IEEE Embedded Systems Letters,2014,6(2):29-32.
[13] HOU Yi,LIU Rongke,PENG Hao,et al.High-throughput GPU-based LDPC decoder architecture for space communication[J].Acta Aeronautica Et Astronautica Sinica,2017,38(1):236-245.(in Chinese)侯毅,刘荣科,彭皓,等.适用于空间通信的LDPC码GPU高速译码架构[J].航空学报,2017,38(1):236-245.
[14] REN Jilin,CHE Shuling,ZHENG Zheng.Decoding of regular LDPC codes accelerated by the GPU[J].Journal of Xidian University,2017,44(3):25-30.(in Chinese)任计林,车书玲,郑征.规则LDPC码在GPU上的加速译码[J].西安电子科技大学学报,2017,44(3):25-30.
[15] LIU Shaoting,WANG Xiaokai,GUO Dabo.Accelerated computational implementation of reconciliation for continuous variable quantum key distribution on GPU[J].Journal on Communications,2017,38(11):171-177.(in Chinese)刘绍婷,王晓凯,郭大波.连续变量量子密钥分发数据协调加速运算的GPU实现[J].通信学报,2017,38(11):171-177.
[16] LIU Zhanxian,LIU Rongke,HOU Yi,et al.High throughput multi-codeword decoder for non-binary LDPC codes on GPU[J].IEEE Communications Letters,2018,22(3):486-489.
[17] VARNICA N,FOSSORIER M P C,KAVCIC A.Augmented belief propagation decoding of low-density parity check codes[J].IEEE Transactions on Communications,2007,55(7):1308-1317.
[18] SCHOLL S,SCHLÄFER P,WEHN N.Saturated min-sum decoding:an afterburner for LDPC decoder hardware[C]//Proceedings of Design,Automation & Test in Europe Conference & Exhibition.Washington D.C.,USA:IEEE Press,2016:1219-1224.
[19] KANG Peng,XIE Yixuan,YANG Lei,et al.Enhanced quasi-maximum likelihood decoding of short LDPC codes based on saturation[EB/OL].[2019-09-31].https://arxiv.org/abs/1810.13111.
[20] MILICEVIC M,FEN C,ZHANG L M,et al.Key reconciliation with low-density parity-check codes for long-distance quantum cryptography[EB/OL].[2019-09-31].https://arxiv.org/abs/1702.07740.
[21] FARBER R.CUDA application design and development[M].San Francisco,USA:Morgan Kaufmann,2011.

选择文件类型/文献管理软件名称

选择包含的内容

基于GPU的LDPC增强准最大似然译码器并行实现

Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder

RichHTML

PDF

可视化

被引次数

摘要/Abstract

引用本文

使用本文

图/表 16

参考文献

相关文章 15

编辑推荐

Metrics

本文评价

[1]	黄正伟, 刘宏伟, 徐渊. 用于IToF传感器的极低功耗RISC-V专用处理器设计[J]. 计算机工程, 2022, 48(9): 146-154.
[2]	奚智雯, 蔡晶晶, 阳文敏, 柴志雷. 基于微服务架构FPGA云平台的并发请求调度机制[J]. 计算机工程, 2022, 48(7): 206-213.
[3]	巩杰, 赵烁, 何虎, 邓宁. 基于FPGA的量化CNN加速系统设计[J]. 计算机工程, 2022, 48(3): 170-174,196.
[4]	黄瑞, 金光浩, 李磊, 姜文超, 宋庆增. 轻量化神经网络加速器的设计与实现[J]. 计算机工程, 2021, 47(9): 185-190,196.
[5]	赵晨园, 李文新, 张庆熙. 一种改进的实时半全局立体匹配算法及硬件实现[J]. 计算机工程, 2021, 47(9): 162-170.
[6]	狄新凯, 杨海钢. 基于FPGA的稀疏化卷积神经网络加速器[J]. 计算机工程, 2021, 47(7): 189-195,204.
[7]	石永泉, 景乃锋. 基于FPGA模拟的阻变神经网络加速器评估方法[J]. 计算机工程, 2021, 47(12): 209-214.
[8]	吴健凤, 郑博文, 聂一, 柴志雷. 基于OpenCL的3DES算法FPGA加速器[J]. 计算机工程, 2021, 47(12): 147-155,162.
[9]	张浩, 魏敬和. 高效率PLB2AXI总线桥的设计与验证[J]. 计算机工程, 2020, 46(8): 228-234.
[10]	宋安, 王琴, 谷大武, 郭筝, 刘军荣, 张驰. 基于FPGA的时钟同步功耗信息采集方法[J]. 计算机工程, 2020, 46(6): 115-121.
[11]	杨冯帆, 常劲帆, 王铮. 一种可实现高精度时间同步的数据传输方法[J]. 计算机工程, 2020, 46(2): 118-125,133.
[12]	李超, 李波, 丁洪伟, 杨志军, 柳虔林. 基于FPGA的战术数据链协议设计与实现[J]. 计算机工程, 2020, 46(10): 173-181.
[13]	薛建伟, 姜爱民. 光学综合孔径原理样机的计算与控制系统[J]. 计算机工程, 2019, 45(8): 107-112.
[14]	李沛南,薛萍,林忱,蒋银坪,孟洪宇. 一种高效片间互联接口协议的设计与实现[J]. 计算机工程, 2018, 44(4): 66-73,80.
[15]	彭海英,杨箭,孙力军. 可快速编码的大围长QC-LDPC码构造方法[J]. 计算机工程, 2018, 44(1): 128-133.

模态框（Modal）标题

选择文件类型/文献管理软件名称

选择包含的内容

基于GPU的LDPC增强准最大似然译码器并行实现

Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder

RichHTML

PDF

可视化

被引次数

摘要/Abstract

引用本文

使用本文

图/表 16

参考文献

相关文章 15

编辑推荐

Metrics

本文评价