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计算机工程 ›› 2011, Vol. 37 ›› Issue (8): 246-248. doi: 10.3969/j.issn.1000-3428.2011.08.086

• 工程应用技术与实现 • 上一篇    下一篇

电子收费系统车载单元LLC子层研究

张 威,李跃辉,景为平   

  1. (南通大学江苏省专用集成电路设计重点实验室,江苏 南通 226019)
  • 出版日期:2011-04-20 发布日期:2012-10-31
  • 作者简介:张 威(1985-),女,硕士研究生,主研方向:集成电路设计;李跃辉,工程师、硕士;景为平,研究员、博士生导师
  • 基金资助:
    中华人民共和国交通运输部基金资助项目(2009-353-332- 290);江苏省交通厅基金资助项目(09X12);江苏省研究生创新工程基金资助项目(CX09S-022Z)

Study on LLC Sub-layer of On-board Unit in ETC System

ZHANG Wei, LI Yue-hui, JING Wei-ping   

  1. (Jiangsu Province Key Laboratory of ASIC, Nantong University, Nantong 226019, China)
  • Online:2011-04-20 Published:2012-10-31

摘要: 采用通用微控制器实现电子收费(ETC)专用短程通信的逻辑链路控制(LLC)子层时存在功耗大、速度慢等缺点。针对该问题,通过研究ETC系统中车载单元LLC子层协议的工作原理,提出以专用逻辑电路实现LLC子层的功能,给出2种类型服务在该层的状态转换方式。利用Verilog HDL在FPGA上实现该层的功能,结果证明了该方法的有效性。

关键词: 电子收费, 专用短程通信, 逻辑链路控制, 状态分析, FPGA实现, Verilog HDL语言

Abstract: There are some disadvantages of high power dissipation, low speed and so on when the general microcontroller is used to implement the Logical Link Control(LLC) sub-layer of Dedicated Short-Range Communication(DSRC) in Electronic Toll Collection(ETC) system. By analyzing working principle of LLC sub-layer protocol of on-board unit in ETC system, this paper proposes a LLC sub-layer protocol which is implemented by specific logical circuit. The state transition modes of two types of services are presented. The function of LLC sub-layer is realized in Verilog HDL, and FPGA experimental results show the effectiveness of the method.

Key words: Electronic Toll Collection(ETC), Dedicated Short-Range Communication(DSRC), Logical Link Control(LLC), state analysis, implementation with FPGA, Verilog HDL

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