[1] Mitra S, Seifert N, Zhang M, et al. Robust System Design with Built-in Soft-error Resilience[J]. Computer, 2005, 38(2): 43-52. [2] 梁华国, 黄正峰, 王 伟, 等. 一种双模互锁的容软错误静态锁存器[J]. 宇航学报, 2009, 30(5): 2020-2024. [3] 陆 阳, 王 强, 张本宏, 等. 计算机系统容错技术研究[J]. 计算机工程, 2010, 36(13): 230-235. [4] Agarwal M, Paul B C, Zhang Ming, et al. Circuit Failure Pre- diction and Its Application to Transistor Aging[C]//Proc. of Very Large Scale Integration Test Symposium. Berkeley, USA: [s. n.], 2007: 277-286. [5] Yan Guihai, Han Yinhe, Li Xiaowei. SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation[J]. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(9): 1627-1640. [6] Vazquez J C, Champac V, Ziesemer A M, et al. Low-sensitivity to Process Variations Aging Sensor for Automotive Safety-critical Applications[C]//Proc. of Very Large Scale Integration Test Symposium. Santa Cruz, USA: [s. n.], 2010: 238-243. [7] Wang L T, McCluskey E J. Concurrent Built-in Logic Block Observer[C]//Proc. of Symposium on Circuits and Systems. [S. l.]: IEEE Press, 1986: 1054-1057. [8] 黄正峰, 梁华国, 陈 田, 等. 一种容软错误的BIST结构[J]. 计算机辅助设计与图形学学报, 2009, 21(1): 33-36, 43. [9] Sato T, Kunitake Y. A Simple Flip-flop Circuit for Typical-case Designs for DFM[C]//Proc. of Symposium on Quality Electronic Design. San Jose, USA: [s. n.], 2007: 539-544. [10] Fazeli M, Patooghy A, Miremadi S G, et al. Feedback Redundancy: A Power Efficient SEU-tolerant Latch Design for Deep Submicron Technologies[C]//Proc. of the 37th International Conference on Dependable Systems and Networks. Edinburgh, UK: [s. n.], 2007: 276-285. [11] Messenger G C. Collection of Charge on Junction Nodes from Ion Tracks[J]. IEEE Trans. on Nuclear Science, 1982, 29(6): 2024- 2031.
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