计算机工程 ›› 2012, Vol. 38 ›› Issue (9): 237-239.doi: 10.3969/j.issn.1000-3428.2012.09.073

• 工程应用技术与实现 • 上一篇    下一篇

基于多层AHB架构的多核SoC设计

刘继尧,刘雷波,尹首一,魏少军   

  1. (清华大学微电子学研究所信息科学与技术国家实验室,北京 100084)
  • 收稿日期:2011-08-22 出版日期:2012-05-05 发布日期:2012-05-05
  • 作者简介:刘继尧(1985-),男,硕士研究生,主研方向:多核片上系统;刘雷波,副教授;尹首一,副研究员;魏少军,教授、博士生导师
  • 基金项目:
    国家“863”计划基金资助重点项目(2009AA011702); 国家自然科学基金资助项目(60803018)

Design of Multi-core SoC Based on Multi-layer AHB Architecture

LIU Ji-yao, LIU Lei-bo, YIN Shou-yi, WEI Shao-jun   

  1. (National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China)
  • Received:2011-08-22 Online:2012-05-05 Published:2012-05-05

摘要: 设计并实现一个基于多层AHB架构的多核异构片上系统。以ARM和DSP处理器为核心,对控制密集型任务和计算密集型任务进行合理分配并高效执行。采用分布式存储和共享存储相结合的存储器配置方案,保证数据完整性与程序并行性。利用基于多层AHB的开关矩阵结构,使不同主设备在不竞争同一个从设备时可并行访问总线。实验结果表明,该系统的资源消耗和延迟较小,可支持较大的网络带宽。

关键词: 多核, 片上总线, 片上系统, 片上通信

Abstract: In this paper, a heterogeneous multi-core System on a Chip(SoC) based on multi-layer AHB architecture is proposed. The processor subsystem consists of an ARM processor and two DSP processors. Therefore both control-intensive tasks and computing-intensive tasks are executed efficiently. Both distributed memory and shared memory system are employed in order to achieve the trade-off between data integration and program parallelism. The communication mechanism is based on switching matrix architecture. As long as there is no competition for one certain slave, different masters are able to access the bus simultaneously. Experimental result shows that this system has low resource consumption and latency. It is able to achieve high bandwidth.

Key words: multi-core, on-chip bus, System on a Chip(SoC), on-chip communication

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